--- np2/i386c/ia32/cpu_io.c	2004/02/20 16:09:04	1.4
+++ np2/i386c/ia32/cpu_io.c	2005/03/12 12:32:54	1.7
@@ -1,4 +1,4 @@
-/*	$Id: cpu_io.c,v 1.4 2004/02/20 16:09:04 monaka Exp $	*/
+/*	$Id: cpu_io.c,v 1.7 2005/03/12 12:32:54 monaka Exp $	*/
 
 /*
  * Copyright (c) 2003 NONAKA Kimihiro
@@ -12,8 +12,6 @@
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
@@ -28,13 +26,16 @@
  */
 
 #include "compiler.h"
+
 #include "cpu.h"
 #include "pccore.h"
 #include "iocore.h"
+#include "memory.h"
 
+static void IOOUTCALL check_io(UINT port, UINT len) GCC_ATTR_REGPARM;
 
-static void
-check_io(UINT port, UINT len)
+static void IOOUTCALL
+check_io(UINT port, UINT len) 
 {
 	UINT off;
 	UINT8 bit;
@@ -63,6 +64,28 @@ check_io(UINT port, UINT len)
 	}
 }
 
+#if defined(IA32_SUPPORT_DEBUG_REGISTER) && CPU_FAMILY >= 5
+INLINE static void IOOUTCALL
+check_ioport_break_point(UINT port, UINT length)
+{
+	int i;
+
+	if (CPU_STAT_BP && !(CPU_EFLAG & RF_FLAG)) {
+		for (i = 0; i < CPU_DEBUG_REG_INDEX_NUM; i++) {
+			if ((CPU_STAT_BP & (1 << i))
+			 && (CPU_DR7_GET_RW(i) == CPU_DR7_RW_IO)
+
+			 && ((port <= CPU_DR(i) && port + length > CPU_DR(i))
+			  || (port > CPU_DR(i) && port <= CPU_DR(i) + CPU_DR7_GET_LEN(i)))) {
+				CPU_STAT_BP_EVENT |= CPU_STAT_BP_EVENT_B(i);
+			}
+		}
+	}
+}
+#else
+#define	check_ioport_break_point(port, length)
+#endif
+
 UINT8
 cpu_in(UINT port)
 {
@@ -70,6 +93,7 @@ cpu_in(UINT port)
 	if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) {
 		check_io(port, 1);
 	}
+	check_ioport_break_point(port, 1);
 	return iocore_inp8(port);
 }
 
@@ -80,6 +104,7 @@ cpu_in_w(UINT port)
 	if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) {
 		check_io(port, 2);
 	}
+	check_ioport_break_point(port, 2);
 	return iocore_inp16(port);
 }
 
@@ -90,6 +115,7 @@ cpu_in_d(UINT port)
 	if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) {
 		check_io(port, 4);
 	}
+	check_ioport_break_point(port, 4);
 	return iocore_inp32(port);
 }
 
@@ -100,6 +126,7 @@ cpu_out(UINT port, UINT8 data)
 	if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) {
 		check_io(port, 1);
 	}
+	check_ioport_break_point(port, 1);
 	iocore_out8(port, data);
 }
 
@@ -110,6 +137,7 @@ cpu_out_w(UINT port, UINT16 data)
 	if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) {
 		check_io(port, 2);
 	}
+	check_ioport_break_point(port, 2);
 	iocore_out16(port, data);
 }
 
@@ -120,5 +148,6 @@ cpu_out_d(UINT port, UINT32 data)
 	if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL > CPU_STAT_IOPL))) {
 		check_io(port, 4);
 	}
+	check_ioport_break_point(port, 4);
 	iocore_out32(port, data);
 }