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Diff for /np2/i386c/ia32/cpu_mem.c between versions 1.15 and 1.17

version 1.15, 2004/03/23 15:29:34 version 1.17, 2004/03/25 15:08:32
Line 265  cpu_prefetch(UINT32 address) Line 265  cpu_prefetch(UINT32 address)
         UINT offset = address & CPU_PREFETCHQ_MASK;          UINT offset = address & CPU_PREFETCHQ_MASK;
         UINT length = CPU_PREFETCH_QUEUE_LENGTH - offset;          UINT length = CPU_PREFETCH_QUEUE_LENGTH - offset;
   
         cpu_memory_access_la_region(address, length, CPU_PAGE_READ_CODE, CPU_STAT_USER_MODE, CPU_PREFETCHQ + offset);          cpu_memory_access_la_region(address, length, CPU_PAGE_READ_CODE|CPU_STAT_USER_MODE, CPU_PREFETCHQ + offset);
         CPU_PREFETCHQ_REMAIN = (SINT8)length;          CPU_PREFETCHQ_REMAIN = (SINT8)length;
 }  }
   
Line 359  cpu_codefetch(UINT32 offset) Line 359  cpu_codefetch(UINT32 offset)
 #else   /* !IA32_SUPPORT_PREFETCH_QUEUE */  #else   /* !IA32_SUPPORT_PREFETCH_QUEUE */
                 if (!CPU_STAT_PAGING)                  if (!CPU_STAT_PAGING)
                         return cpu_memoryread(addr);                          return cpu_memoryread(addr);
                 return cpu_lcmemoryread(addr);                  return cpu_linear_memory_read_b(addr, CPU_PAGE_READ_CODE | CPU_STAT_USER_MODE);
 #endif  /* IA32_SUPPORT_PREFETCH_QUEUE */  #endif  /* IA32_SUPPORT_PREFETCH_QUEUE */
         }          }
         EXCEPTION(GP_EXCEPTION, 0);          EXCEPTION(GP_EXCEPTION, 0);
Line 394  cpu_codefetch_w(UINT32 offset) Line 394  cpu_codefetch_w(UINT32 offset)
 #else   /* !IA32_SUPPORT_PREFETCH_QUEUE */  #else   /* !IA32_SUPPORT_PREFETCH_QUEUE */
                 if (!CPU_STAT_PAGING)                  if (!CPU_STAT_PAGING)
                         return cpu_memoryread_w(addr);                          return cpu_memoryread_w(addr);
                 return cpu_lcmemoryread_w(addr);                  return cpu_linear_memory_read_w(addr, CPU_PAGE_READ_CODE | CPU_STAT_USER_MODE);
 #endif  /* IA32_SUPPORT_PREFETCH_QUEUE */  #endif  /* IA32_SUPPORT_PREFETCH_QUEUE */
         }          }
         EXCEPTION(GP_EXCEPTION, 0);          EXCEPTION(GP_EXCEPTION, 0);
Line 441  cpu_codefetch_d(UINT32 offset) Line 441  cpu_codefetch_d(UINT32 offset)
                                 cpu_prefetch(addr);                                  cpu_prefetch(addr);
                                 v += (UINT32)cpu_prefetchq(addr) << 24;                                  v += (UINT32)cpu_prefetchq(addr) << 24;
                                 break;                                  break;
   
                           default:
                                   ia32_panic("cpu_codefetch_d: remain bytes is invalid");
                                   v = 0; /* compiler happy */
                                   break;
                         }                          }
                         return v;                          return v;
                 }                  }
 #else   /* !IA32_SUPPORT_PREFETCH_QUEUE */  #else   /* !IA32_SUPPORT_PREFETCH_QUEUE */
                 if (!CPU_STAT_PAGING)                  if (!CPU_STAT_PAGING)
                         return cpu_memoryread_d(addr);                          return cpu_memoryread_d(addr);
                 return cpu_lcmemoryread_d(addr);                  return cpu_linear_memory_read_d(addr, CPU_PAGE_READ_CODE | CPU_STAT_USER_MODE);
 #endif  /* IA32_SUPPORT_PREFETCH_QUEUE */  #endif  /* IA32_SUPPORT_PREFETCH_QUEUE */
         }          }
         EXCEPTION(GP_EXCEPTION, 0);          EXCEPTION(GP_EXCEPTION, 0);
Removed from v.1.15  
changed lines
  Added in v.1.17

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