np2/i386c/ia32/cpu_mem.mcr - diff

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version 1.1, 2004/03/23 15:29:34	version 1.3, 2004/03/25 15:08:32
Line 63 cpu_vmemoryread_##width(int idx, UINT32	Line 63 cpu_vmemoryread_##width(int idx, UINT32
check_memory_break_point(addr, (length), CPU_DR7_RW_RO); \	check_memory_break_point(addr, (length), CPU_DR7_RW_RO); \
if (!CPU_STAT_PAGING) \	if (!CPU_STAT_PAGING) \
return cpu_memoryread_##width(addr); \	return cpu_memoryread_##width(addr); \
return cpu_lmemoryread_##width(addr, CPU_STAT_USER_MODE); \	return cpu_linear_memory_read_##width(addr, CPU_PAGE_READ_DATA \| CPU_STAT_USER_MODE); \
\	\
range_failure: \	range_failure: \
if (idx == CPU_SS_INDEX) { \	if (idx == CPU_SS_INDEX) { \
Line 113 cpu_vmemorywrite_##width(int idx, UINT32	Line 113 cpu_vmemorywrite_##width(int idx, UINT32
if (!CPU_STAT_PAGING) { \	if (!CPU_STAT_PAGING) { \
cpu_memorywrite_##width(addr, value); \	cpu_memorywrite_##width(addr, value); \
} else { \	} else { \
cpu_lmemorywrite_##width(addr, value, CPU_STAT_USER_MODE); \	cpu_linear_memory_write_##width(addr, value, CPU_PAGE_WRITE_DATA \| CPU_STAT_USER_MODE); \
} \	} \
return; \	return; \
\	\
Line 167 cpu_memory_access_va_RMW_##width(int idx	Line 167 cpu_memory_access_va_RMW_##width(int idx
res = (*func)(dst, arg); \	res = (*func)(dst, arg); \
cpu_memorywrite_##width(addr, res); \	cpu_memorywrite_##width(addr, res); \
} else { \	} else { \
dst = cpu_memory_access_la_RMW(addr, length, CPU_STAT_USER_MODE, func, arg); \	dst = cpu_memory_access_la_RMW_##width(addr, func, arg); \
} \	} \
return dst; \	return dst; \
\	\

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