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| version 1.3, 2004/01/14 16:14:49 | version 1.4, 2004/01/23 14:33:26 |
|---|---|
| Line 30 | Line 30 |
| #include "compiler.h" | #include "compiler.h" |
| #include "cpu.h" | #include "cpu.h" |
| #include "memory.h" | |
| #ifdef USE_FPU | #ifdef USE_FPU |
| #include "instructions/fpu/fpu.h" | #include "instructions/fpu/fpu.h" |
| #endif | #endif |
| #if 0 | |
| extern BOOL is_a20(void); /* in ../cpuio.c */ | |
| #endif | |
| char *cpu_reg2str(void) | char *cpu_reg2str(void) |
| { | { |
| Line 115 char *fpu_reg2str(void) | Line 113 char *fpu_reg2str(void) |
| } | } |
| #endif | #endif |
| #if 0 | |
| static char *a20str(void) | static char *a20str(void) |
| { | { |
| static char buf[32]; | static char buf[32]; |
| sprintf(buf, "a20line=%s\n", is_a20() ? "enable" : "disable"); | sprintf(buf, "a20line=%s\n", CPU_STAT_ADRSMASK == 0xffffffff ? "enable" : "disable"); |
| return buf; | return buf; |
| } | } |
| Line 189 void put_cpuinfo(void) | Line 186 void put_cpuinfo(void) |
| printf(buf); | printf(buf); |
| } | } |
| #endif | |
| void | |
| memory_dump(int idx, DWORD madr) | |
| { | |
| DWORD addr; | |
| size_t size; | |
| unsigned char buf[16]; | |
| size_t s, i; | |
| BYTE p; | |
| if (madr < 0x80) { | |
| size = madr + 0x80; | |
| addr = 0; | |
| } else { | |
| size = 0x100; | |
| addr = madr - 0x80; | |
| } | |
| VERBOSE(("memory dump\n-- \n")); | |
| for (s = 0; s < size; s++) { | |
| if ((s % 16) == 0) { | |
| VERBOSE(("%08x: ", addr + s)); | |
| memset(buf, '.', sizeof(buf)); | |
| } | |
| p = cpu_vmemoryread(idx, addr + s); | |
| VERBOSE(("%02x ", p)); | |
| if (p >= 0x20 && p <= 0x7e) | |
| buf[s % 16] = p; | |
| if ((s % 16) == 15) { | |
| VERBOSE(("| ")); | |
| for (i = 0; i < sizeof(buf); i++) | |
| VERBOSE(("%c", buf[i])); | |
| VERBOSE(("\n")); | |
| } | |
| } | |
| } | |
| void | |
| gdtr_dump(DWORD base, DWORD limit) | |
| { | |
| DWORD v[2]; | |
| DWORD i; | |
| VERBOSE(("GDTR_DUMP: GDTR_BASE = 0x%08x, GDTR_LIMIT = 0x%04x",base,limit)); | |
| for (i = 0; i < limit; i += 8) { | |
| v[0] = cpu_lmemoryread_d(base + i); | |
| v[1] = cpu_lmemoryread_d(base + i + 4); | |
| VERBOSE(("GDTR_DUMP: %08x: %08x%08x", base + i, v[0], v[1])); | |
| } | |
| } | |
| void | |
| ldtr_dump(DWORD base, DWORD limit) | |
| { | |
| DWORD v[2]; | |
| DWORD i; | |
| VERBOSE(("LDTR_DUMP: LDTR_BASE = 0x%08x, LDTR_LIMIT = 0x%04x",base,limit)); | |
| for (i = 0; i < limit; i += 8) { | |
| v[0] = cpu_lmemoryread_d(base + i); | |
| v[1] = cpu_lmemoryread_d(base + i + 4); | |
| VERBOSE(("LDTR_DUMP: %08x: %08x%08x", base + i, v[0], v[1])); | |
| } | |
| } | |
| void | |
| idtr_dump(DWORD base, DWORD limit) | |
| { | |
| DWORD v[2]; | |
| DWORD i; | |
| VERBOSE(("IDTR_DUMP: IDTR_BASE = 0x%08x, IDTR_LIMIT = 0x%04x",base,limit)); | |
| for (i = 0; i < limit; i += 8) { | |
| v[0] = cpu_lmemoryread_d(base + i); | |
| v[1] = cpu_lmemoryread_d(base + i + 4); | |
| VERBOSE(("IDTR_DUMP: %08x: %08x%08x", base + i, v[0], v[1])); | |
| } | |
| } | |
| void | |
| tr_dump(WORD selector, DWORD base, DWORD limit) | |
| { | |
| DWORD v; | |
| DWORD i; | |
| VERBOSE(("TR_DUMP: selector = %04x", selector)); | |
| for (i = 0; i < limit; i += 4) { | |
| v = cpu_lmemoryread_d(base + i); | |
| VERBOSE(("TR_DUMP: %08x: %08x", base + i, v)); | |
| } | |
| } | |
| DWORD | |
| pde_dump(DWORD base, int idx) | |
| { | |
| DWORD paddr; | |
| DWORD v; | |
| int i; | |
| if (idx < 0 && idx > -8192) { | |
| idx = -idx; | |
| VERBOSE(("PDE_DUMP: address = 0x%08x, num = %d", base, idx)); | |
| for (i = 0; i < idx; i++) { | |
| paddr = (base & CPU_CR3_PD_MASK) | (idx << 2); | |
| v = cpu_memoryread_d(paddr); | |
| VERBOSE(("PDE_DUMP: 0x%08x: %08x", paddr, v)); | |
| } | |
| paddr = 0; | |
| } else if (idx < 8192) { | |
| VERBOSE(("PDE_DUMP: address = 0x%08x", base)); | |
| paddr = (base & CPU_CR3_PD_MASK) | (idx << 2); | |
| v = cpu_memoryread_d(paddr); | |
| VERBOSE(("PDE_DUMP: 0x%08x: %08x", paddr, v)); | |
| } else { | |
| paddr = 0; | |
| } | |
| return paddr; | |
| } | |
| DWORD | |
| convert_laddr_to_paddr(DWORD laddr) | |
| { | |
| DWORD paddr; /* physical address */ | |
| DWORD pde_addr; /* page directory entry address */ | |
| DWORD pde; /* page directory entry */ | |
| DWORD pte_addr; /* page table entry address */ | |
| DWORD pte; /* page table entry */ | |
| pde_addr = (CPU_CR3 & CPU_CR3_PD_MASK) | ((laddr >> 20) & 0xffc); | |
| pde = cpu_memoryread_d(pde_addr); | |
| if ((CPU_CR4 & CPU_CR4_PSE) && (pde & CPU_PDE_PAGE_SIZE)) { | |
| /* 4MB page size */ | |
| paddr = (pde & CPU_PDE_4M_BASEADDR_MASK) | (laddr & 0x003fffff); | |
| } else { | |
| /* 4KB page size */ | |
| pte_addr = (pde & CPU_PDE_BASEADDR_MASK) | ((laddr >> 10) & 0xffc); | |
| pte = cpu_memoryread_d(pte_addr); | |
| paddr = (pte & CPU_PTE_BASEADDR_MASK) | (laddr & 0x00000fff); | |
| } | |
| return paddr; | |
| } | |
| DWORD | |
| convert_vaddr_to_paddr(unsigned int idx, DWORD offset) | |
| { | |
| descriptor_t *sdp; | |
| DWORD laddr; | |
| if (idx < CPU_SEGREG_NUM) { | |
| sdp = &CPU_STAT_SREG(idx); | |
| if (sdp->valid) { | |
| laddr = CPU_STAT_SREGBASE(idx) + offset; | |
| return convert_laddr_to_paddr(laddr); | |
| } | |
| } | |
| return 0; | |
| } |