--- np2/i386c/ia32/debug.c	2003/12/08 00:55:31	1.1
+++ np2/i386c/ia32/debug.c	2004/01/23 14:33:26	1.4
@@ -1,4 +1,4 @@
-/*	$Id: debug.c,v 1.1 2003/12/08 00:55:31 yui Exp $	*/
+/*	$Id: debug.c,v 1.4 2004/01/23 14:33:26 monaka Exp $	*/
 
 /*
  * Copyright (c) 2002-2003 NONAKA Kimihiro
@@ -27,14 +27,16 @@
  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
+#include "compiler.h"
+
 #include "cpu.h"
+#include "memory.h"
 #ifdef USE_FPU
- #include "instructions/fpu/fpu.h"
+#include "instructions/fpu/fpu.h"
 #endif
 
-extern BOOL is_a20(void);	/* in ../cpuio.c */
 
-static char *cpu_reg2str(void)
+char *cpu_reg2str(void)
 {
   static char buf[512];
 
@@ -45,38 +47,40 @@ static char *cpu_reg2str(void)
     "eflag=%08x "
 /* ID VIP VIF AC VM RF NT IOPL OF DF IF TF SF ZF AF PF CF */
       "[ ID=%d VIP=%d VIF=%d AC=%d VM=%d RF=%d NT=%d IOPL=%d%d %s %s %s TF=%d %s %s %s %s %s ]\n"
-    "gdtr=%08x:%04x idtr=%08x:%04x ldtr=%04x tr=%04x\n"
+    "gdtr=%08x:%04x idtr=%08x:%04x\n"
+    "ldtr=%04x(%08x:%04x) tr=%04x(%08x:%04x)\n"
     "cr0=%08x cr1=%08x cr2=%08x cr3=%08x cr4=%08x mxcsr=%08x\n",
-    I286_EAX, I286_EBX, I286_ECX, I286_EDX, I286_ESI, I286_EDI,
-    I286_EIP, I286_ESP, I286_EBP, CPU_PREV_EIP,
-    I286_CS, I286_SS, I286_DS, I286_ES, I286_FS, I286_GS,
-    I286_EFLAG,
-      (I286_EFLAG & ID_FLAG) != 0,
-      (I286_EFLAG & VIP_FLAG) != 0,
-      (I286_EFLAG & VIF_FLAG) != 0,
-      (I286_EFLAG & AC_FLAG) != 0,
-      (I286_EFLAG & VM_FLAG) != 0,
-      (I286_EFLAG & RF_FLAG) != 0,
-      (I286_EFLAG & NT_FLAG) != 0,
-      I286_EFLAG >> 13 & 1,
-      I286_EFLAG >> 12 & 1,
-      I286_EFLAG & O_FLAG ? "OV" : "NV",
-      I286_EFLAG & D_FLAG ? "UP" : "DN",
-      I286_EFLAG & I_FLAG ? "DI" : "EI",
-      (I286_EFLAG & T_FLAG) != 0,
-      I286_EFLAG & S_FLAG ? "NG" : "PL",
-      I286_EFLAG & Z_FLAG ? "ZR" : "NZ",
-      I286_EFLAG & A_FLAG ? "AC" : "NA",
-      I286_EFLAG & P_FLAG ? "PE" : "PO",
-      I286_EFLAG & C_FLAG ? "CY" : "NC",
-    CPU_GDTR_BASE, CPU_GDTR_LIMIT, CPU_IDTR_BASE, CPU_IDTR_LIMIT, CPU_LDTR, CPU_TR,
+    CPU_EAX, CPU_EBX, CPU_ECX, CPU_EDX, CPU_ESI, CPU_EDI,
+    CPU_EIP, CPU_ESP, CPU_EBP, CPU_PREV_EIP,
+    CPU_CS, CPU_SS, CPU_DS, CPU_ES, CPU_FS, CPU_GS,
+    CPU_EFLAG,
+      (CPU_EFLAG & ID_FLAG) != 0,
+      (CPU_EFLAG & VIP_FLAG) != 0,
+      (CPU_EFLAG & VIF_FLAG) != 0,
+      (CPU_EFLAG & AC_FLAG) != 0,
+      (CPU_EFLAG & VM_FLAG) != 0,
+      (CPU_EFLAG & RF_FLAG) != 0,
+      (CPU_EFLAG & NT_FLAG) != 0,
+      CPU_EFLAG >> 13 & 1,
+      CPU_EFLAG >> 12 & 1,
+      CPU_EFLAG & O_FLAG ? "OV" : "NV",
+      CPU_EFLAG & D_FLAG ? "UP" : "DN",
+      CPU_EFLAG & I_FLAG ? "DI" : "EI",
+      (CPU_EFLAG & T_FLAG) != 0,
+      CPU_EFLAG & S_FLAG ? "NG" : "PL",
+      CPU_EFLAG & Z_FLAG ? "ZR" : "NZ",
+      CPU_EFLAG & A_FLAG ? "AC" : "NA",
+      CPU_EFLAG & P_FLAG ? "PE" : "PO",
+      CPU_EFLAG & C_FLAG ? "CY" : "NC",
+    CPU_GDTR_BASE, CPU_GDTR_LIMIT, CPU_IDTR_BASE, CPU_IDTR_LIMIT,
+    CPU_LDTR, CPU_LDTR_BASE, CPU_LDTR_LIMIT, CPU_TR, CPU_TR_BASE, CPU_TR_LIMIT,
     CPU_CR0, CPU_CR1, CPU_CR2, CPU_CR3, CPU_CR4, CPU_MXCSR);
 
   return buf;
 }
 
 #ifdef USE_FPU
-static char *fpu_reg2str(void)
+char *fpu_reg2str(void)
 {
   static char buf[512];
   char tmp[128];
@@ -113,7 +117,7 @@ static char *a20str(void)
 {
   static char buf[32];
 
-  sprintf(buf, "a20line=%s\n", is_a20() ? "enable" : "disable");
+  sprintf(buf, "a20line=%s\n", CPU_STAT_ADRSMASK == 0xffffffff ? "enable" : "disable");
   return buf;
 }
 
@@ -160,7 +164,7 @@ void FASTCALL msgbox_mem(DWORD no)
   strcat(buf, fpu_reg2str());
   strcat(buf, "\n");
 #endif
-  strcat(buf, mem2str(I286_CS, I286_IP));
+  strcat(buf, mem2str(CPU_CS, CPU_IP));
   strcat(buf, "\n");
   sprintf(tmp, "no=%08x\n", no);
   strcat(buf, tmp);
@@ -182,3 +186,167 @@ void put_cpuinfo(void)
 
   printf(buf);
 }
+
+void
+memory_dump(int idx, DWORD madr)
+{
+	DWORD addr;
+	size_t size;
+	unsigned char buf[16];
+	size_t s, i;
+	BYTE p;
+
+	if (madr < 0x80) {
+		size = madr + 0x80;
+		addr = 0;
+	} else {
+		size = 0x100;
+		addr = madr - 0x80;
+	}
+	VERBOSE(("memory dump\n-- \n"));
+	for (s = 0; s < size; s++) {
+		if ((s % 16) == 0) {
+			VERBOSE(("%08x: ", addr + s));
+			memset(buf, '.', sizeof(buf));
+		}
+
+		p = cpu_vmemoryread(idx, addr + s);
+		VERBOSE(("%02x ", p));
+		if (p >= 0x20 && p <= 0x7e)
+			buf[s % 16] = p;
+
+		if ((s % 16) == 15) {
+			VERBOSE(("| "));
+			for (i = 0; i < sizeof(buf); i++)
+				VERBOSE(("%c", buf[i]));
+			VERBOSE(("\n"));
+		}
+	}
+}
+
+void
+gdtr_dump(DWORD base, DWORD limit)
+{
+	DWORD v[2];
+	DWORD i;
+
+	VERBOSE(("GDTR_DUMP: GDTR_BASE = 0x%08x, GDTR_LIMIT = 0x%04x",base,limit));
+
+	for (i = 0; i < limit; i += 8) {
+		v[0] = cpu_lmemoryread_d(base + i);
+		v[1] = cpu_lmemoryread_d(base + i + 4);
+		VERBOSE(("GDTR_DUMP: %08x: %08x%08x", base + i, v[0], v[1]));
+	}
+}
+
+void
+ldtr_dump(DWORD base, DWORD limit)
+{
+	DWORD v[2];
+	DWORD i;
+
+	VERBOSE(("LDTR_DUMP: LDTR_BASE = 0x%08x, LDTR_LIMIT = 0x%04x",base,limit));
+
+	for (i = 0; i < limit; i += 8) {
+		v[0] = cpu_lmemoryread_d(base + i);
+		v[1] = cpu_lmemoryread_d(base + i + 4);
+		VERBOSE(("LDTR_DUMP: %08x: %08x%08x", base + i, v[0], v[1]));
+	}
+}
+
+void
+idtr_dump(DWORD base, DWORD limit)
+{
+	DWORD v[2];
+	DWORD i;
+
+	VERBOSE(("IDTR_DUMP: IDTR_BASE = 0x%08x, IDTR_LIMIT = 0x%04x",base,limit));
+
+	for (i = 0; i < limit; i += 8) {
+		v[0] = cpu_lmemoryread_d(base + i);
+		v[1] = cpu_lmemoryread_d(base + i + 4);
+		VERBOSE(("IDTR_DUMP: %08x: %08x%08x", base + i, v[0], v[1]));
+	}
+}
+
+void
+tr_dump(WORD selector, DWORD base, DWORD limit)
+{
+	DWORD v;
+	DWORD i;
+
+	VERBOSE(("TR_DUMP: selector = %04x", selector));
+
+	for (i = 0; i < limit; i += 4) {
+		v = cpu_lmemoryread_d(base + i);
+		VERBOSE(("TR_DUMP: %08x: %08x", base + i, v));
+	}
+}
+
+DWORD
+pde_dump(DWORD base, int idx)
+{
+	DWORD paddr;
+	DWORD v;
+	int i;
+
+	if (idx < 0 && idx > -8192) {
+		idx = -idx;
+		VERBOSE(("PDE_DUMP: address = 0x%08x, num = %d", base, idx));
+		for (i = 0; i < idx; i++) {
+			paddr = (base & CPU_CR3_PD_MASK) | (idx << 2);
+			v = cpu_memoryread_d(paddr);
+			VERBOSE(("PDE_DUMP: 0x%08x: %08x", paddr, v));
+		}
+		paddr = 0;
+	} else if (idx < 8192) {
+		VERBOSE(("PDE_DUMP: address = 0x%08x", base));
+		paddr = (base & CPU_CR3_PD_MASK) | (idx << 2);
+		v = cpu_memoryread_d(paddr);
+		VERBOSE(("PDE_DUMP: 0x%08x: %08x", paddr, v));
+	} else {
+		paddr = 0;
+	}
+
+	return paddr;
+}
+
+DWORD
+convert_laddr_to_paddr(DWORD laddr)
+{
+	DWORD paddr;	/* physical address */
+	DWORD pde_addr;	/* page directory entry address */
+	DWORD pde;	/* page directory entry */
+	DWORD pte_addr;	/* page table entry address */
+	DWORD pte;	/* page table entry */
+
+	pde_addr = (CPU_CR3 & CPU_CR3_PD_MASK) | ((laddr >> 20) & 0xffc);
+	pde = cpu_memoryread_d(pde_addr);
+
+	if ((CPU_CR4 & CPU_CR4_PSE) && (pde & CPU_PDE_PAGE_SIZE)) {
+		/* 4MB page size */
+		paddr = (pde & CPU_PDE_4M_BASEADDR_MASK) | (laddr & 0x003fffff);
+	} else {
+		/* 4KB page size */
+		pte_addr = (pde & CPU_PDE_BASEADDR_MASK) | ((laddr >> 10) & 0xffc);
+		pte = cpu_memoryread_d(pte_addr);
+		paddr = (pte & CPU_PTE_BASEADDR_MASK) | (laddr & 0x00000fff);
+	}
+	return paddr;
+}
+
+DWORD
+convert_vaddr_to_paddr(unsigned int idx, DWORD offset)
+{
+	descriptor_t *sdp;
+	DWORD laddr;
+
+	if (idx < CPU_SEGREG_NUM) {
+		sdp = &CPU_STAT_SREG(idx);
+		if (sdp->valid) {
+			laddr = CPU_STAT_SREGBASE(idx) + offset;
+			return convert_laddr_to_paddr(laddr);
+		}
+	}
+	return 0;
+}