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| version 1.1, 2003/12/08 00:55:31 | version 1.3, 2003/12/22 18:00:31 |
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| Line 32 | Line 32 |
| #include "ia32.mcr" | #include "ia32.mcr" |
| CPU_REGS cpu_regs; | |
| CPU_SYSREGS cpu_sysregs; | |
| CPU_STAT cpu_stat; | |
| CPU_INST cpu_inst; | |
| CPU_INST cpu_inst_default; | |
| I386CORE i386core; | I386CORE i386core; |
| // #if defined(USE_ASM) | |
| BYTE iflags[] = { | BYTE iflags[] = { |
| 0x44, 0x00, 0x00, 0x04, 0x00, 0x04, 0x04, 0x00, | 0x44, 0x00, 0x00, 0x04, 0x00, 0x04, 0x04, 0x00, |
| 0x00, 0x04, 0x04, 0x00, 0x04, 0x00, 0x00, 0x04, | 0x00, 0x04, 0x04, 0x00, 0x04, 0x00, 0x00, 0x04, |
| Line 74 BYTE iflags[] = { | Line 68 BYTE iflags[] = { |
| 0x84, 0x80, 0x80, 0x84, 0x80, 0x84, 0x84, 0x80, | 0x84, 0x80, 0x80, 0x84, 0x80, 0x84, 0x84, 0x80, |
| 0x80, 0x84, 0x84, 0x80, 0x84, 0x80, 0x80, 0x84, | 0x80, 0x84, 0x84, 0x80, 0x84, 0x80, 0x80, 0x84, |
| }; | }; |
| // #endif /* USE_ASM */ | |
| BYTE *reg8_b20[0x100]; | BYTE *reg8_b20[0x100]; |
| BYTE *reg8_b53[0x100]; | BYTE *reg8_b53[0x100]; |
| Line 89 ia32_init(void) | Line 82 ia32_init(void) |
| { | { |
| int i; | int i; |
| memset(&cpu_regs, 0, sizeof(cpu_regs)); | memset(&i386core, 0, sizeof(i386core)); |
| memset(&cpu_sysregs, 0, sizeof(cpu_sysregs)); | CPU_STATSAVE.cpu_inst_default.seg_base = (DWORD)-1; |
| memset(&cpu_stat, 0, sizeof(cpu_stat)); | |
| memset(&cpu_inst_default, 0, sizeof(cpu_inst_default)); | |
| CPU_EDX = (CPU_FAMILY << 8) | (CPU_MODEL << 4) | CPU_STEPPING; | CPU_EDX = (CPU_FAMILY << 8) | (CPU_MODEL << 4) | CPU_STEPPING; |
| CPU_EFLAG = 2; | CPU_EFLAG = 2; |