| version 1.8, 2004/02/06 16:49:51 | version 1.20, 2008/01/25 17:49:46 | 
| Line 12 | Line 12 | 
 | * 2. Redistributions in binary form must reproduce the above copyright | * 2. Redistributions in binary form must reproduce the above copyright | 
 | *    notice, this list of conditions and the following disclaimer in the | *    notice, this list of conditions and the following disclaimer in the | 
 | *    documentation and/or other materials provided with the distribution. | *    documentation and/or other materials provided with the distribution. | 
 | * 3. The name of the author may not be used to endorse or promote products |  | 
 | *    derived from this software without specific prior written permission. |  | 
 | * | * | 
 | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR | * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR | 
 | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES | * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES | 
| Line 31 | Line 29 | 
 | #include "cpu.h" | #include "cpu.h" | 
 | #include "ia32.mcr" | #include "ia32.mcr" | 
 |  |  | 
 |  |  | 
 | I386CORE        i386core; | I386CORE        i386core; | 
 |  |  | 
| BYTE    *reg8_b20[0x100]; | UINT8   *reg8_b20[0x100]; | 
| BYTE    *reg8_b53[0x100]; | UINT8   *reg8_b53[0x100]; | 
| WORD    *reg16_b20[0x100]; | UINT16  *reg16_b20[0x100]; | 
| WORD    *reg16_b53[0x100]; | UINT16  *reg16_b53[0x100]; | 
| DWORD   *reg32_b20[0x100]; | UINT32  *reg32_b20[0x100]; | 
| DWORD   *reg32_b53[0x100]; | UINT32  *reg32_b53[0x100]; | 
|  |  | 
 |  |  | 
 | void | void | 
 | ia32_init(void) | ia32_init(void) | 
| Line 78  ia32_init(void) | Line 74  ia32_init(void) | 
 | } | } | 
 |  |  | 
 | resolve_init(); | resolve_init(); | 
 | #if defined(IA32_SUPPORT_TLB) |  | 
 | tlb_init(); |  | 
 | #endif |  | 
 | #ifdef USE_FPU |  | 
 | fpu_init(); |  | 
 | #endif |  | 
 | } | } | 
 |  |  | 
 | void | void | 
| Line 91  ia32_setextsize(UINT32 size) | Line 81  ia32_setextsize(UINT32 size) | 
 | { | { | 
 |  |  | 
 | if (CPU_EXTMEMSIZE != size) { | if (CPU_EXTMEMSIZE != size) { | 
| if (CPU_EXTMEM) { | UINT8 *extmem; | 
| _MFREE(CPU_EXTMEM); | extmem = CPU_EXTMEM; | 
| CPU_EXTMEM = NULL; | if (extmem != NULL) { | 
|  | _MFREE(extmem); | 
|  | extmem = NULL; | 
|  | } | 
|  | if (size != 0) { | 
|  | extmem = (UINT8 *)_MALLOC(size + 16, "EXTMEM"); | 
|  | } | 
|  | if (extmem != NULL) { | 
|  | ZeroMemory(extmem, size + 16); | 
|  | CPU_EXTMEM = extmem; | 
|  | CPU_EXTMEMSIZE = size; | 
|  | CPU_EXTMEMBASE = CPU_EXTMEM - 0x100000; | 
|  | CPU_EXTLIMIT16 = min(size + 0x100000, 0xf00000); | 
|  | CPU_EXTLIMIT = size + 0x100000; | 
 | } | } | 
| if (size) { | else { | 
| CPU_EXTMEM = (BYTE *)_MALLOC(size + 16, "EXTMEM"); | CPU_EXTMEM = NULL; | 
| if (CPU_EXTMEM == NULL) { | CPU_EXTMEMSIZE = 0; | 
| size = 0; | CPU_EXTMEMBASE = NULL; | 
| } | CPU_EXTLIMIT16 = 0; | 
| ZeroMemory(CPU_EXTMEM, size + 16); | CPU_EXTLIMIT = 0; | 
 | } | } | 
 | CPU_EXTMEMSIZE = size; |  | 
 | } | } | 
 |  | CPU_EMSPTR[0] = mem + 0xc0000; | 
 |  | CPU_EMSPTR[1] = mem + 0xc4000; | 
 |  | CPU_EMSPTR[2] = mem + 0xc8000; | 
 |  | CPU_EMSPTR[3] = mem + 0xcc000; | 
 |  | } | 
 |  |  | 
 |  | void | 
 |  | ia32_setemm(UINT frame, UINT32 addr) { | 
 |  |  | 
 |  | BYTE    *ptr; | 
 |  |  | 
 |  | frame &= 3; | 
 |  | if (addr < USE_HIMEM) { | 
 |  | ptr = mem + addr; | 
 |  | } | 
 |  | else if ((addr - 0x100000 + 0x4000) <= CPU_EXTMEMSIZE) { | 
 |  | ptr = CPU_EXTMEM + (addr - 0x100000); | 
 |  | } | 
 |  | else { | 
 |  | ptr = mem + 0xc0000 + (frame << 14); | 
 |  | } | 
 |  | CPU_EMSPTR[frame] = ptr; | 
 | } | } | 
 |  |  | 
 |  |  | 
 | /* | /* | 
 | * モード遷移 | * モード遷移 | 
 | */ | */ | 
| Line 152  change_vm(BOOL onoff) | Line 177  change_vm(BOOL onoff) | 
 | CPU_STAT_VM86 = onoff; | CPU_STAT_VM86 = onoff; | 
 | if (onoff) { | if (onoff) { | 
 | for (i = 0; i < CPU_SEGREG_NUM; i++) { | for (i = 0; i < CPU_SEGREG_NUM; i++) { | 
 |  | CPU_STAT_SREGLIMIT(i) = 0xffff; | 
 | CPU_SET_SEGREG(i, CPU_REGS_SREG(i)); | CPU_SET_SEGREG(i, CPU_REGS_SREG(i)); | 
 | } | } | 
 | CPU_INST_OP32 = CPU_INST_AS32 = | CPU_INST_OP32 = CPU_INST_AS32 = | 
| Line 169  change_vm(BOOL onoff) | Line 195  change_vm(BOOL onoff) | 
 | * flags | * flags | 
 | */ | */ | 
 | static void | static void | 
| modify_eflags(DWORD new_flags, DWORD mask) | modify_eflags(UINT32 new_flags, UINT32 mask) | 
 | { | { | 
| DWORD orig = CPU_EFLAG; | UINT32 orig = CPU_EFLAG; | 
 |  |  | 
 | new_flags &= ALL_EFLAG; | new_flags &= ALL_EFLAG; | 
 | mask &= ALL_EFLAG; | mask &= ALL_EFLAG; | 
| CPU_EFLAG = (REAL_EFLAGREG & ~mask) | (new_flags & mask) | 0x2; | CPU_EFLAG = (REAL_EFLAGREG & ~mask) | (new_flags & mask); | 
 |  |  | 
 | CPU_OV = CPU_FLAG & O_FLAG; | CPU_OV = CPU_FLAG & O_FLAG; | 
 | CPU_TRAP = (CPU_FLAG & (I_FLAG|T_FLAG)) == (I_FLAG|T_FLAG); | CPU_TRAP = (CPU_FLAG & (I_FLAG|T_FLAG)) == (I_FLAG|T_FLAG); | 
| if ((orig ^ CPU_EFLAG) & VM_FLAG) { | if (CPU_STAT_PM) { | 
| if (CPU_EFLAG & VM_FLAG) { | if ((orig ^ CPU_EFLAG) & VM_FLAG) { | 
| change_vm(1); | if (CPU_EFLAG & VM_FLAG) { | 
| } else { | change_vm(1); | 
| change_vm(0); | } else { | 
|  | change_vm(0); | 
|  | } | 
 | } | } | 
 | } | } | 
 | } | } | 
 |  |  | 
 | void | void | 
| set_flags(WORD new_flags, WORD mask) | set_flags(UINT16 new_flags, UINT16 mask) | 
 | { | { | 
 |  |  | 
 | mask &= I_FLAG|IOPL_FLAG; | mask &= I_FLAG|IOPL_FLAG; | 
| mask |= (SZAPC_FLAG|T_FLAG|D_FLAG|O_FLAG|NT_FLAG); | mask |= SZAPC_FLAG|T_FLAG|D_FLAG|O_FLAG|NT_FLAG; | 
| modify_eflags(new_flags, 0xffff0000|mask); | modify_eflags(new_flags, mask); | 
 | } | } | 
 |  |  | 
 | void | void | 
| set_eflags(DWORD new_flags, DWORD mask) | set_eflags(UINT32 new_flags, UINT32 mask) | 
 | { | { | 
 |  |  | 
 | mask &= I_FLAG|IOPL_FLAG|RF_FLAG|VM_FLAG|VIF_FLAG|VIP_FLAG; | mask &= I_FLAG|IOPL_FLAG|RF_FLAG|VM_FLAG|VIF_FLAG|VIP_FLAG; |