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Diff for /np2/i386c/ia32/ia32.mcr between versions 1.13 and 1.17

version 1.13, 2004/02/20 16:09:04 version 1.17, 2004/03/21 21:30:49
Line 92  do { \ Line 92  do { \
                 EXCEPTION(GP_EXCEPTION, 0); \                  EXCEPTION(GP_EXCEPTION, 0); \
         } \          } \
         CPU_EIP = __new_ip; \          CPU_EIP = __new_ip; \
           CPU_PREFETCH_CLEAR(); \
 } while (/*CONSTCOND*/ 0)  } while (/*CONSTCOND*/ 0)
   
 #define ADD_EIP(v) \  #define ADD_EIP(v) \
Line 687  do { \ Line 688  do { \
  */   */
 #define REGPUSH(reg, clock) \  #define REGPUSH(reg, clock) \
 do { \  do { \
         CPU_SP -= 2; \          UINT16 new_sp = CPU_SP - 2; \
         cpu_vmemorywrite_w(CPU_SS_INDEX, CPU_SP, reg); \          cpu_vmemorywrite_w(CPU_SS_INDEX, new_sp, reg); \
           CPU_SP = new_sp; \
         CPU_WORKCLOCK(clock); \          CPU_WORKCLOCK(clock); \
 } while (/*CONSTCOND*/ 0)  } while (/*CONSTCOND*/ 0)
   
 #define REGPUSH_32(reg, clock) \  #define REGPUSH_32(reg, clock) \
 do { \  do { \
         CPU_ESP -= 4; \          UINT32 new_esp = CPU_ESP - 4; \
         cpu_vmemorywrite_d(CPU_SS_INDEX, CPU_ESP, reg); \          cpu_vmemorywrite_d(CPU_SS_INDEX, new_esp, reg); \
           CPU_ESP = new_esp; \
         CPU_WORKCLOCK(clock); \          CPU_WORKCLOCK(clock); \
 } while (/*CONSTCOND*/ 0)  } while (/*CONSTCOND*/ 0)
   
 #define REGPUSH0(reg) \  #define REGPUSH0(reg) \
 do { \  do { \
         CPU_SP -= 2; \          UINT16 new_sp = CPU_SP - 2; \
         cpu_vmemorywrite_w(CPU_SS_INDEX, CPU_SP, (UINT16)reg); \          cpu_vmemorywrite_w(CPU_SS_INDEX, new_sp, (UINT16)reg); \
           CPU_SP = new_sp; \
 } while (/*CONSTCOND*/ 0)  } while (/*CONSTCOND*/ 0)
   
 /* Operand Size == 16 && Stack Size == 32 */  /* Operand Size == 16 && Stack Size == 32 */
 #define REGPUSH0_16_32(reg) \  #define REGPUSH0_16_32(reg) \
 do { \  do { \
         CPU_ESP -= 2; \          UINT32 new_esp = CPU_ESP - 2; \
         cpu_vmemorywrite_w(CPU_SS_INDEX, CPU_ESP, (UINT16)reg); \          cpu_vmemorywrite_w(CPU_SS_INDEX, new_esp, (UINT16)reg); \
           CPU_ESP = new_esp; \
 } while (/*CONSTCOND*/ 0)  } while (/*CONSTCOND*/ 0)
   
 /* Operand Size == 32 && Stack Size == 16 */  /* Operand Size == 32 && Stack Size == 16 */
 #define REGPUSH0_32_16(reg) \  #define REGPUSH0_32_16(reg) \
 do { \  do { \
         CPU_SP -= 4; \          UINT16 new_sp = CPU_SP - 4; \
         cpu_vmemorywrite_d(CPU_SS_INDEX, CPU_SP, reg); \          cpu_vmemorywrite_d(CPU_SS_INDEX, new_sp, reg); \
           CPU_SP = new_sp; \
 } while (/*CONSTCOND*/ 0)  } while (/*CONSTCOND*/ 0)
   
 #define REGPUSH0_32(reg) \  #define REGPUSH0_32(reg) \
 do { \  do { \
         CPU_ESP -= 4; \          UINT32 new_esp = CPU_ESP - 4; \
         cpu_vmemorywrite_d(CPU_SS_INDEX, CPU_ESP, reg); \          cpu_vmemorywrite_d(CPU_SS_INDEX, new_esp, reg); \
           CPU_ESP = new_esp; \
 } while (/*CONSTCOND*/ 0)  } while (/*CONSTCOND*/ 0)
   
 #define PUSH0_16(reg) \  #define PUSH0_16(reg) \
Line 864  do { \ Line 871  do { \
         __ip = __CBD(cpu_codefetch(CPU_EIP)); \          __ip = __CBD(cpu_codefetch(CPU_EIP)); \
         __ip++; \          __ip++; \
         ADD_EIP(__ip); \          ADD_EIP(__ip); \
           CPU_PREFETCH_CLEAR(); \
 } while (/*CONSTCOND*/ 0)  } while (/*CONSTCOND*/ 0)
   
 #define JMPNEAR(clock) \  #define JMPNEAR(clock) \
Line 873  do { \ Line 881  do { \
         __ip = __CWDE(cpu_codefetch_w(CPU_EIP)); \          __ip = __CWDE(cpu_codefetch_w(CPU_EIP)); \
         __ip += 2; \          __ip += 2; \
         ADD_EIP(__ip); \          ADD_EIP(__ip); \
           CPU_PREFETCH_CLEAR(); \
 } while (/*CONSTCOND*/ 0)  } while (/*CONSTCOND*/ 0)
   
 #define JMPNEAR_4(clock) \  #define JMPNEAR_4(clock) \
Line 882  do { \ Line 891  do { \
         __ip = cpu_codefetch_d(CPU_EIP); \          __ip = cpu_codefetch_d(CPU_EIP); \
         __ip += 4; \          __ip += 4; \
         ADD_EIP(__ip); \          ADD_EIP(__ip); \
           CPU_PREFETCH_CLEAR(); \
 } while (/*CONSTCOND*/ 0)  } while (/*CONSTCOND*/ 0)
   
   #if !defined(IA32_SUPPORT_PREFETCH_QUEUE)
 #define JMPNOP(clock, d) \  #define JMPNOP(clock, d) \
 do { \  do { \
         CPU_WORKCLOCK(clock); \          CPU_WORKCLOCK(clock); \
         ADD_EIP((d)); \          ADD_EIP((d)); \
 } while (/*CONSTCOND*/ 0)  } while (/*CONSTCOND*/ 0)
   #else
   #define JMPNOP(clock, d) \
   do { \
           CPU_WORKCLOCK(clock); \
           CPU_PREFETCHQ_REMAIN -= (d); \
           ADD_EIP((d)); \
   } while (/*CONSTCOND*/ 0)
   #endif
   
   
   /*
    * conditions
    */
   #define CC_O    (CPU_OV)
   #define CC_NO   (!CPU_OV)
   #define CC_C    (CPU_FLAGL & C_FLAG)
   #define CC_NC   (!(CPU_FLAGL & C_FLAG))
   #define CC_Z    (CPU_FLAGL & Z_FLAG)
   #define CC_NZ   (!(CPU_FLAGL & Z_FLAG))
   #define CC_NA   (CPU_FLAGL & (Z_FLAG | C_FLAG))
   #define CC_A    (!(CPU_FLAGL & (Z_FLAG | C_FLAG)))
   #define CC_S    (CPU_FLAGL & S_FLAG)
   #define CC_NS   (!(CPU_FLAGL & S_FLAG))
   #define CC_P    (CPU_FLAGL & P_FLAG)
   #define CC_NP   (!(CPU_FLAGL & P_FLAG))
   #define CC_L    (((CPU_FLAGL & S_FLAG) == 0) != (CPU_OV == 0))
   #define CC_NL   (((CPU_FLAGL & S_FLAG) == 0) == (CPU_OV == 0))
   #define CC_LE   ((CPU_FLAGL & Z_FLAG) || \
                                   (((CPU_FLAGL & S_FLAG) == 0) != (CPU_OV == 0)))
   #define CC_NLE  ((!(CPU_FLAGL & Z_FLAG)) && \
                                   (((CPU_FLAGL & S_FLAG) == 0) == (CPU_OV == 0)))
   
   
 /*  /*
Removed from v.1.13  
changed lines
  Added in v.1.17

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