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| version 1.3, 2004/01/15 15:49:15 | version 1.12, 2004/02/19 03:04:01 |
|---|---|
| Line 58 do { \ | Line 58 do { \ |
| (q) = __tmp; \ | (q) = __tmp; \ |
| } while (/*CONSTCOND*/ 0) | } while (/*CONSTCOND*/ 0) |
| /* | |
| * bswap | |
| */ | |
| #if defined(bswap32) && !defined(USE_ASM_BSWAP) | |
| #define BSWAP_DWORD(v) bswap32(v) | |
| #else /* !bswap32 || USE_ASM_BSWAP */ | |
| INLINE static DWORD | |
| BSWAP_DWORD(DWORD val) | |
| { | |
| #if defined(__GNUC__) && (defined(i386) || defined(__i386__)) | |
| __asm__ __volatile__ ( | |
| #if defined(USE_ASM_BSWAP) | |
| "bswap %0" | |
| #else /* !USE_ASM_BSWAP */ | |
| "rorw $8, %w1\n\t" | |
| "rorl $16, %1\n\t" | |
| "rorw $8, %w1\n\t" | |
| #endif /* USE_ASM_BSWAP */ | |
| : "=r" (val) : "0" (val)); | |
| return val; | |
| #else /* !(__GNUC__ && (i386 || __i386__)) */ | |
| DWORD v; | |
| v = (val & 0x000000ff) << 24; | |
| v |= (val & 0x0000ff00) << 8; | |
| v |= (val & 0x00ff0000) >> 8; | |
| v |= (val & 0xff000000) >> 24; | |
| return v; | |
| #endif /* __GNUC__ && (i386 || __i386__) */ | |
| } | |
| #endif /* bswap32 && !USE_ASM_BSWAP */ | |
| /* | /* |
| * clock | * clock |
| */ | */ |
| #ifndef DONT_USE_NEVENT | |
| #define CPU_WORKCLOCK(clock) \ | #define CPU_WORKCLOCK(clock) \ |
| do { \ | do { \ |
| CPU_REMCLOCK -= (clock); \ | CPU_REMCLOCK -= (clock); \ |
| Line 111 do { \ | Line 79 do { \ |
| CPU_REMCLOCK = 0; \ | CPU_REMCLOCK = 0; \ |
| } \ | } \ |
| } while (/*CONSTCOND*/ 0) | } while (/*CONSTCOND*/ 0) |
| #endif | |
| /* | |
| * instruction pointer | |
| */ | |
| #define SET_EIP(v) \ | #define SET_EIP(v) \ |
| do { \ | do { \ |
| DWORD __new_ip = (v); \ | DWORD __new_ip = (v); \ |
| if (!CPU_INST_OP32) { \ | |
| __new_ip &= 0x0000ffff; \ | |
| } \ | |
| if (__new_ip > CPU_STAT_CS_LIMIT) { \ | if (__new_ip > CPU_STAT_CS_LIMIT) { \ |
| VERBOSE(("SET_EIP: new_ip = %08x, limit = %08x", __new_ip, CPU_STAT_CS_LIMIT)); \ | |
| EXCEPTION(GP_EXCEPTION, 0); \ | EXCEPTION(GP_EXCEPTION, 0); \ |
| } \ | } \ |
| CPU_EIP = __new_ip; \ | CPU_EIP = __new_ip; \ |
| Line 129 do { \ | Line 97 do { \ |
| #define ADD_EIP(v) \ | #define ADD_EIP(v) \ |
| do { \ | do { \ |
| DWORD __tmp_ip = CPU_EIP + (v); \ | DWORD __tmp_ip = CPU_EIP + (v); \ |
| if (!CPU_INST_OP32) { \ | if (!CPU_STATSAVE.cpu_inst_default.op_32) { \ |
| __tmp_ip &= 0x0000ffff; \ | __tmp_ip &= 0xffff; \ |
| } \ | |
| if (__tmp_ip > CPU_STAT_CS_LIMIT) { \ | |
| EXCEPTION(GP_EXCEPTION, 0); \ | |
| } \ | } \ |
| CPU_EIP = __tmp_ip; \ | CPU_EIP = __tmp_ip; \ |
| } while (/*CONSTCOND*/ 0) | } while (/*CONSTCOND*/ 0) |
| Line 360 do { \ | Line 325 do { \ |
| do { \ | do { \ |
| (d) |= (s); \ | (d) |= (s); \ |
| CPU_OV = 0; \ | CPU_OV = 0; \ |
| CPU_FLAGL = szpcflag[(BYTE)(d)] & P_FLAG; \ | CPU_FLAGL = (BYTE)(szpcflag[(BYTE)(d)] & P_FLAG); \ |
| if ((d) == 0) { \ | if ((d) == 0) { \ |
| CPU_FLAGL |= Z_FLAG; \ | CPU_FLAGL |= Z_FLAG; \ |
| } \ | } \ |
| Line 435 do { \ | Line 400 do { \ |
| (r) = (d) - (s) - __c; \ | (r) = (d) - (s) - __c; \ |
| CPU_OV = ((d) ^ (r)) & ((d) ^ (s)) & 0x80000000; \ | CPU_OV = ((d) ^ (r)) & ((d) ^ (s)) & 0x80000000; \ |
| CPU_FLAGL = (BYTE)(((r) ^ (d) ^ (s)) & A_FLAG); \ | CPU_FLAGL = (BYTE)(((r) ^ (d) ^ (s)) & A_FLAG); \ |
| if ((d) < (s) + __c) { \ | if ((!__c && (d) < (s)) || (__c && (d) <= (s))) { \ |
| CPU_FLAGL |= C_FLAG; \ | CPU_FLAGL |= C_FLAG; \ |
| } \ | } \ |
| if ((r) == 0) { \ | if ((r) == 0) { \ |
| Line 465 do { \ | Line 430 do { \ |
| do { \ | do { \ |
| (d) &= (s); \ | (d) &= (s); \ |
| CPU_OV = 0; \ | CPU_OV = 0; \ |
| CPU_FLAGL = szpcflag[(BYTE)(d)] & P_FLAG; \ | CPU_FLAGL = (BYTE)(szpcflag[(BYTE)(d)] & P_FLAG); \ |
| if ((d) == 0) { \ | if ((d) == 0) { \ |
| CPU_FLAGL |= Z_FLAG; \ | CPU_FLAGL |= Z_FLAG; \ |
| } \ | } \ |
| Line 529 do { \ | Line 494 do { \ |
| do { \ | do { \ |
| (d) ^= (s); \ | (d) ^= (s); \ |
| CPU_OV = 0; \ | CPU_OV = 0; \ |
| CPU_FLAGL = szpcflag[(BYTE)(d)] & P_FLAG; \ | CPU_FLAGL = (BYTE)(szpcflag[(BYTE)(d)] & P_FLAG); \ |
| if ((d) == 0) { \ | if ((d) == 0) { \ |
| CPU_FLAGL |= Z_FLAG; \ | CPU_FLAGL |= Z_FLAG; \ |
| } \ | } \ |
| Line 633 do { \ | Line 598 do { \ |
| do { \ | do { \ |
| CPU_FLAGL &= (Z_FLAG | S_FLAG | A_FLAG | P_FLAG); \ | CPU_FLAGL &= (Z_FLAG | S_FLAG | A_FLAG | P_FLAG); \ |
| (r) = (SQWORD)(d) * (SQWORD)(s); \ | (r) = (SQWORD)(d) * (SQWORD)(s); \ |
| CPU_OV = (DWORD)(((r) + 0x80000000ULL) >> 32); \ | CPU_OV = (DWORD)(((r) + QWORD_CONST(0x80000000)) >> 32); \ |
| if (CPU_OV) { \ | if (CPU_OV) { \ |
| CPU_FLAGL |= C_FLAG; \ | CPU_FLAGL |= C_FLAG; \ |
| } \ | } \ |
| Line 740 do { \ | Line 705 do { \ |
| #define REGPUSH0(reg) \ | #define REGPUSH0(reg) \ |
| do { \ | do { \ |
| CPU_SP -= 2; \ | CPU_SP -= 2; \ |
| cpu_vmemorywrite_w(CPU_SS_INDEX, CPU_SP, reg); \ | cpu_vmemorywrite_w(CPU_SS_INDEX, CPU_SP, (WORD)reg); \ |
| } while (/*CONSTCOND*/ 0) | } while (/*CONSTCOND*/ 0) |
| /* Operand Size == 16 && Stack Size == 32 */ | /* Operand Size == 16 && Stack Size == 32 */ |
| #define REGPUSH0_16_32(reg) \ | #define REGPUSH0_16_32(reg) \ |
| do { \ | do { \ |
| CPU_ESP -= 2; \ | CPU_ESP -= 2; \ |
| cpu_vmemorywrite_w(CPU_SS_INDEX, CPU_ESP, reg); \ | cpu_vmemorywrite_w(CPU_SS_INDEX, CPU_ESP, (WORD)reg); \ |
| } while (/*CONSTCOND*/ 0) | } while (/*CONSTCOND*/ 0) |
| /* Operand Size == 32 && Stack Size == 16 */ | /* Operand Size == 32 && Stack Size == 16 */ |
| Line 763 do { \ | Line 728 do { \ |
| cpu_vmemorywrite_d(CPU_SS_INDEX, CPU_ESP, reg); \ | cpu_vmemorywrite_d(CPU_SS_INDEX, CPU_ESP, reg); \ |
| } while (/*CONSTCOND*/ 0) | } while (/*CONSTCOND*/ 0) |
| #define SP_PUSH(reg, clock) \ | |
| do { \ | |
| WORD sp = CPU_SP; \ | |
| CPU_SP -= 2; \ | |
| cpu_vmemorywrite_w(CPU_SS_INDEX, CPU_SP, sp); \ | |
| CPU_WORKCLOCK(clock); \ | |
| } while (/*CONSTCOND*/ 0) | |
| #define SP_PUSH0(reg) \ | |
| do { \ | |
| WORD sp = CPU_SP; \ | |
| CPU_SP -= 2; \ | |
| cpu_vmemorywrite_w(CPU_SS_INDEX, CPU_SP, sp); \ | |
| } while (/*CONSTCOND*/ 0) | |
| #define SP_PUSH0_16_32(reg) \ | |
| do { \ | |
| WORD sp = CPU_SP; \ | |
| CPU_ESP -= 2; \ | |
| cpu_vmemorywrite_w(CPU_SS_INDEX, CPU_ESP, sp); \ | |
| } while (/*CONSTCOND*/ 0) | |
| #define ESP_PUSH(reg, clock) \ | |
| do { \ | |
| DWORD esp = CPU_ESP; \ | |
| CPU_ESP -= 4; \ | |
| cpu_vmemorywrite_d(CPU_SS_INDEX, CPU_ESP, esp); \ | |
| CPU_WORKCLOCK(clock); \ | |
| } while (/*CONSTCOND*/ 0) | |
| #define ESP_PUSH0_32_16(reg) \ | |
| do { \ | |
| DWORD esp = CPU_ESP; \ | |
| CPU_SP -= 4; \ | |
| cpu_vmemorywrite_d(CPU_SS_INDEX, CPU_SP, esp); \ | |
| } while (/*CONSTCOND*/ 0) | |
| #define ESP_PUSH0_32(reg) \ | |
| do { \ | |
| DWORD esp = CPU_ESP; \ | |
| CPU_ESP -= 4; \ | |
| cpu_vmemorywrite_d(CPU_SS_INDEX, CPU_ESP, esp); \ | |
| } while (/*CONSTCOND*/ 0) | |
| #define PUSH0_16(reg) \ | #define PUSH0_16(reg) \ |
| do { \ | do { \ |
| if (!CPU_STAT_SS32) { \ | if (!CPU_STAT_SS32) { \ |
| Line 834 do { \ | Line 755 do { \ |
| } \ | } \ |
| } while (/*CONSTCOND*/ 0) | } while (/*CONSTCOND*/ 0) |
| #define SP_PUSH0_16(reg) \ | |
| do { \ | |
| WORD sp = CPU_SP; \ | |
| if (!CPU_STAT_SS32) { \ | |
| CPU_SP -= 2; \ | |
| cpu_vmemorywrite_w(CPU_SS_INDEX, CPU_SP, sp); \ | |
| } else { \ | |
| CPU_ESP -= 2; \ | |
| cpu_vmemorywrite_w(CPU_SS_INDEX, CPU_ESP, sp); \ | |
| } \ | |
| } while (/*CONSTCOND*/ 0) | |
| #define SP_PUSH0_32(reg) \ | |
| do { \ | |
| DWORD esp = CPU_ESP; \ | |
| if (CPU_STAT_SS32) { \ | |
| CPU_ESP -= 4; \ | |
| cpu_vmemorywrite_d(CPU_SS_INDEX, CPU_ESP, esp); \ | |
| } else { \ | |
| CPU_SP -= 4; \ | |
| cpu_vmemorywrite_d(CPU_SS_INDEX, CPU_SP, esp); \ | |
| } \ | |
| } while (/*CONSTCOND*/ 0) | |
| #define REGPOP(reg, clock) \ | #define REGPOP(reg, clock) \ |
| do { \ | do { \ |
| (reg) = cpu_vmemoryread_w(CPU_SS_INDEX, CPU_SP); \ | (reg) = cpu_vmemoryread_w(CPU_SS_INDEX, CPU_SP); \ |
| Line 914 do { \ | Line 811 do { \ |
| } \ | } \ |
| } while (/*CONSTCOND*/ 0) | } while (/*CONSTCOND*/ 0) |
| #define SP_POP0_16(reg) \ | /* |
| * stack pointer | |
| */ | |
| #define SP_PUSH_16(reg) \ | |
| do { \ | do { \ |
| WORD sp = CPU_SP; \ | |
| if (!CPU_STAT_SS32) { \ | if (!CPU_STAT_SS32) { \ |
| (reg) = cpu_vmemoryread_w(CPU_SS_INDEX, CPU_SP); \ | REGPUSH0(sp); \ |
| } else { \ | } else { \ |
| (reg) = cpu_vmemoryread_w(CPU_SS_INDEX, CPU_ESP); \ | REGPUSH0_16_32(sp); \ |
| } \ | } \ |
| } while (/*CONSTCOND*/ 0) | } while (/*CONSTCOND*/ 0) |
| #define ESP_POP0_32(reg) \ | #define ESP_PUSH_32(reg) \ |
| do { \ | do { \ |
| if (CPU_STAT_SS32) { \ | DWORD sp = CPU_ESP; \ |
| (reg) = cpu_vmemoryread_d(CPU_SS_INDEX, CPU_ESP); \ | if (!CPU_STAT_SS32) { \ |
| REGPUSH0_32_16(sp); \ | |
| } else { \ | |
| REGPUSH0_32(sp); \ | |
| } \ | |
| } while (/*CONSTCOND*/ 0) | |
| #define SP_POP_16(reg) \ | |
| do { \ | |
| DWORD sp; \ | |
| if (!CPU_STAT_SS32) { \ | |
| sp = CPU_SP; \ | |
| } else { \ | |
| sp = CPU_ESP; \ | |
| } \ | |
| CPU_SP = cpu_vmemoryread_w(CPU_SS_INDEX, sp); \ | |
| } while (/*CONSTCOND*/ 0) | |
| #define ESP_POP_32(reg) \ | |
| do { \ | |
| DWORD sp; \ | |
| if (!CPU_STAT_SS32) { \ | |
| sp = CPU_SP; \ | |
| } else { \ | } else { \ |
| (reg) = cpu_vmemoryread_d(CPU_SS_INDEX, CPU_SP); \ | sp = CPU_ESP; \ |
| } \ | } \ |
| CPU_ESP = cpu_vmemoryread_d(CPU_SS_INDEX, sp); \ | |
| } while (/*CONSTCOND*/ 0) | } while (/*CONSTCOND*/ 0) |
| /* | /* |
| * jump | * jump |
| */ | */ |
| Line 968 do { \ | Line 893 do { \ |
| ADD_EIP((d)); \ | ADD_EIP((d)); \ |
| } while (/*CONSTCOND*/ 0) | } while (/*CONSTCOND*/ 0) |
| /* instruction check */ | |
| /* | |
| * instruction check | |
| */ | |
| #include "ia32xc.mcr" | #include "ia32xc.mcr" |
| #endif /* IA32_CPU_IA32_MCR__ */ | #endif /* IA32_CPU_IA32_MCR__ */ |