--- np2/i386c/ia32/ia32.mcr	2004/02/20 16:09:04	1.13
+++ np2/i386c/ia32/ia32.mcr	2004/03/21 21:30:49	1.17
@@ -1,4 +1,4 @@
-/*	$Id: ia32.mcr,v 1.13 2004/02/20 16:09:04 monaka Exp $	*/
+/*	$Id: ia32.mcr,v 1.17 2004/03/21 21:30:49 yui Exp $	*/
 
 /*
  * Copyright (c) 2002-2003 NONAKA Kimihiro
@@ -92,6 +92,7 @@ do { \
 		EXCEPTION(GP_EXCEPTION, 0); \
 	} \
 	CPU_EIP = __new_ip; \
+	CPU_PREFETCH_CLEAR(); \
 } while (/*CONSTCOND*/ 0)
 
 #define	ADD_EIP(v) \
@@ -687,42 +688,48 @@ do { \
  */
 #define	REGPUSH(reg, clock) \
 do { \
-	CPU_SP -= 2; \
-	cpu_vmemorywrite_w(CPU_SS_INDEX, CPU_SP, reg); \
+	UINT16 new_sp = CPU_SP - 2; \
+	cpu_vmemorywrite_w(CPU_SS_INDEX, new_sp, reg); \
+	CPU_SP = new_sp; \
 	CPU_WORKCLOCK(clock); \
 } while (/*CONSTCOND*/ 0)
 
 #define	REGPUSH_32(reg, clock) \
 do { \
-	CPU_ESP -= 4; \
-	cpu_vmemorywrite_d(CPU_SS_INDEX, CPU_ESP, reg); \
+	UINT32 new_esp = CPU_ESP - 4; \
+	cpu_vmemorywrite_d(CPU_SS_INDEX, new_esp, reg); \
+	CPU_ESP = new_esp; \
 	CPU_WORKCLOCK(clock); \
 } while (/*CONSTCOND*/ 0)
 
 #define	REGPUSH0(reg) \
 do { \
-	CPU_SP -= 2; \
-	cpu_vmemorywrite_w(CPU_SS_INDEX, CPU_SP, (UINT16)reg); \
+	UINT16 new_sp = CPU_SP - 2; \
+	cpu_vmemorywrite_w(CPU_SS_INDEX, new_sp, (UINT16)reg); \
+	CPU_SP = new_sp; \
 } while (/*CONSTCOND*/ 0)
 
 /* Operand Size == 16 && Stack Size == 32 */
 #define	REGPUSH0_16_32(reg) \
 do { \
-	CPU_ESP -= 2; \
-	cpu_vmemorywrite_w(CPU_SS_INDEX, CPU_ESP, (UINT16)reg); \
+	UINT32 new_esp = CPU_ESP - 2; \
+	cpu_vmemorywrite_w(CPU_SS_INDEX, new_esp, (UINT16)reg); \
+	CPU_ESP = new_esp; \
 } while (/*CONSTCOND*/ 0)
 
 /* Operand Size == 32 && Stack Size == 16 */
 #define	REGPUSH0_32_16(reg) \
 do { \
-	CPU_SP -= 4; \
-	cpu_vmemorywrite_d(CPU_SS_INDEX, CPU_SP, reg); \
+	UINT16 new_sp = CPU_SP - 4; \
+	cpu_vmemorywrite_d(CPU_SS_INDEX, new_sp, reg); \
+	CPU_SP = new_sp; \
 } while (/*CONSTCOND*/ 0)
 
 #define	REGPUSH0_32(reg) \
 do { \
-	CPU_ESP -= 4; \
-	cpu_vmemorywrite_d(CPU_SS_INDEX, CPU_ESP, reg); \
+	UINT32 new_esp = CPU_ESP - 4; \
+	cpu_vmemorywrite_d(CPU_SS_INDEX, new_esp, reg); \
+	CPU_ESP = new_esp; \
 } while (/*CONSTCOND*/ 0)
 
 #define	PUSH0_16(reg) \
@@ -864,6 +871,7 @@ do { \
 	__ip = __CBD(cpu_codefetch(CPU_EIP)); \
 	__ip++; \
 	ADD_EIP(__ip); \
+	CPU_PREFETCH_CLEAR(); \
 } while (/*CONSTCOND*/ 0)
 
 #define	JMPNEAR(clock) \
@@ -873,6 +881,7 @@ do { \
 	__ip = __CWDE(cpu_codefetch_w(CPU_EIP)); \
 	__ip += 2; \
 	ADD_EIP(__ip); \
+	CPU_PREFETCH_CLEAR(); \
 } while (/*CONSTCOND*/ 0)
 
 #define	JMPNEAR_4(clock) \
@@ -882,13 +891,46 @@ do { \
 	__ip = cpu_codefetch_d(CPU_EIP); \
 	__ip += 4; \
 	ADD_EIP(__ip); \
+	CPU_PREFETCH_CLEAR(); \
 } while (/*CONSTCOND*/ 0)
 
+#if !defined(IA32_SUPPORT_PREFETCH_QUEUE)
 #define	JMPNOP(clock, d) \
 do { \
 	CPU_WORKCLOCK(clock); \
 	ADD_EIP((d)); \
 } while (/*CONSTCOND*/ 0)
+#else
+#define	JMPNOP(clock, d) \
+do { \
+	CPU_WORKCLOCK(clock); \
+	CPU_PREFETCHQ_REMAIN -= (d); \
+	ADD_EIP((d)); \
+} while (/*CONSTCOND*/ 0)
+#endif
+
+
+/*
+ * conditions
+ */
+#define	CC_O	(CPU_OV)
+#define	CC_NO	(!CPU_OV)
+#define	CC_C	(CPU_FLAGL & C_FLAG)
+#define	CC_NC	(!(CPU_FLAGL & C_FLAG))
+#define	CC_Z	(CPU_FLAGL & Z_FLAG)
+#define	CC_NZ	(!(CPU_FLAGL & Z_FLAG))
+#define	CC_NA	(CPU_FLAGL & (Z_FLAG | C_FLAG))
+#define	CC_A	(!(CPU_FLAGL & (Z_FLAG | C_FLAG)))
+#define	CC_S	(CPU_FLAGL & S_FLAG)
+#define	CC_NS	(!(CPU_FLAGL & S_FLAG))
+#define	CC_P	(CPU_FLAGL & P_FLAG)
+#define	CC_NP	(!(CPU_FLAGL & P_FLAG))
+#define	CC_L	(((CPU_FLAGL & S_FLAG) == 0) != (CPU_OV == 0))
+#define	CC_NL	(((CPU_FLAGL & S_FLAG) == 0) == (CPU_OV == 0))
+#define	CC_LE	((CPU_FLAGL & Z_FLAG) || \
+				(((CPU_FLAGL & S_FLAG) == 0) != (CPU_OV == 0)))
+#define	CC_NLE	((!(CPU_FLAGL & Z_FLAG)) && \
+				(((CPU_FLAGL & S_FLAG) == 0) == (CPU_OV == 0)))
 
 
 /*