--- np2/i386c/ia32/ia32.mcr	2004/03/08 12:56:22	1.16
+++ np2/i386c/ia32/ia32.mcr	2005/03/12 12:32:54	1.22
@@ -1,4 +1,4 @@
-/*	$Id: ia32.mcr,v 1.16 2004/03/08 12:56:22 monaka Exp $	*/
+/*	$Id: ia32.mcr,v 1.22 2005/03/12 12:32:54 monaka Exp $	*/
 
 /*
  * Copyright (c) 2002-2003 NONAKA Kimihiro
@@ -12,8 +12,6 @@
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
@@ -37,6 +35,13 @@
 #define	__CBD(src)	((UINT32)((SINT8)(src)))
 #define	__CWDE(src)	((SINT16)(src))
 
+#ifndef	PTR_TO_UINT32
+#define	PTR_TO_UINT32(p)	((UINT32)((unsigned long)(p)))
+#endif
+#ifndef	UINT32_TO_PTR
+#define	UINT32_TO_PTR(v)	((void *)((unsigned long)(UINT32)(v)))
+#endif
+
 #define	SWAP_BYTE(p, q) \
 do { \
 	UINT8 __tmp = (p); \
@@ -682,6 +687,21 @@ do { \
 	(s) = __b; \
 } while (/*CONSTCOND*/ 0)
 
+#define	BYTE_NOT(s) \
+do { \
+	(s) ^= 0xff; \
+} while (/*CONSTCOND*/ 0)
+
+#define	WORD_NOT(s) \
+do { \
+	(s) ^= 0xffff; \
+} while (/*CONSTCOND*/ 0)
+
+#define	DWORD_NOT(s) \
+do { \
+	(s) ^= 0xffffffff; \
+} while (/*CONSTCOND*/ 0)
+
 
 /*
  * stack
@@ -904,13 +924,36 @@ do { \
 #define	JMPNOP(clock, d) \
 do { \
 	CPU_WORKCLOCK(clock); \
-	CPU_PREFETCHQ_REMAIN -= (d); \
+	CPU_PREFETCHQ_REMAIN_SUB(d); \
 	ADD_EIP((d)); \
 } while (/*CONSTCOND*/ 0)
 #endif
 
 
 /*
+ * conditions
+ */
+#define	CC_O	(CPU_OV)
+#define	CC_NO	(!CPU_OV)
+#define	CC_C	(CPU_FLAGL & C_FLAG)
+#define	CC_NC	(!(CPU_FLAGL & C_FLAG))
+#define	CC_Z	(CPU_FLAGL & Z_FLAG)
+#define	CC_NZ	(!(CPU_FLAGL & Z_FLAG))
+#define	CC_NA	(CPU_FLAGL & (Z_FLAG | C_FLAG))
+#define	CC_A	(!(CPU_FLAGL & (Z_FLAG | C_FLAG)))
+#define	CC_S	(CPU_FLAGL & S_FLAG)
+#define	CC_NS	(!(CPU_FLAGL & S_FLAG))
+#define	CC_P	(CPU_FLAGL & P_FLAG)
+#define	CC_NP	(!(CPU_FLAGL & P_FLAG))
+#define	CC_L	(((CPU_FLAGL & S_FLAG) == 0) != (CPU_OV == 0))
+#define	CC_NL	(((CPU_FLAGL & S_FLAG) == 0) == (CPU_OV == 0))
+#define	CC_LE	((CPU_FLAGL & Z_FLAG) || \
+				(((CPU_FLAGL & S_FLAG) == 0) != (CPU_OV == 0)))
+#define	CC_NLE	((!(CPU_FLAGL & Z_FLAG)) && \
+				(((CPU_FLAGL & S_FLAG) == 0) == (CPU_OV == 0)))
+
+
+/*
  * instruction check
  */
 #include "ia32xc.mcr"