--- np2/i386c/ia32/instructions/shift_rotate.mcr	2004/03/23 15:29:34	1.9
+++ np2/i386c/ia32/instructions/shift_rotate.mcr	2012/01/08 19:09:40	1.17
@@ -1,5 +1,3 @@
-/*	$Id: shift_rotate.mcr,v 1.9 2004/03/23 15:29:34 monaka Exp $	*/
-
 /*
  * Copyright (c) 2003 NONAKA Kimihiro
  * All rights reserved.
@@ -12,8 +10,6 @@
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
@@ -34,31 +30,28 @@
  * shift/rorate instruction macro
  */
 #define	SHIFT_ROTATE_INSTRUCTION(inst) \
-static UINT32 \
+static UINT32 CPUCALL \
 inst##1(UINT32 src, void *arg) \
 { \
 	UINT32 dst; \
-	(void)arg; \
 	BYTE_##inst##1(dst, src); \
 	return dst; \
 } \
-static UINT32 \
+static UINT32 CPUCALL \
 inst##2(UINT32 src, void *arg) \
 { \
 	UINT32 dst; \
-	(void)arg; \
 	WORD_##inst##1(dst, src); \
 	return dst; \
 } \
-static UINT32 \
+static UINT32 CPUCALL \
 inst##4(UINT32 src, void *arg) \
 { \
 	UINT32 dst; \
-	(void)arg; \
 	DWORD_##inst##1(dst, src); \
 	return dst; \
 } \
-static UINT32 \
+static UINT32 CPUCALL \
 inst##CL1(UINT32 src, void *arg) \
 { \
 	UINT32 cl = PTR_TO_UINT32(arg); \
@@ -66,7 +59,7 @@ inst##CL1(UINT32 src, void *arg) \
 	BYTE_##inst##CL(dst, src, cl); \
 	return dst; \
 } \
-static UINT32 \
+static UINT32 CPUCALL \
 inst##CL2(UINT32 src, void *arg) \
 { \
 	UINT32 cl = PTR_TO_UINT32(arg); \
@@ -74,7 +67,7 @@ inst##CL2(UINT32 src, void *arg) \
 	WORD_##inst##CL(dst, src, cl); \
 	return dst; \
 } \
-static UINT32 \
+static UINT32 CPUCALL \
 inst##CL4(UINT32 src, void *arg) \
 { \
 	UINT32 cl = PTR_TO_UINT32(arg); \
@@ -83,7 +76,7 @@ inst##CL4(UINT32 src, void *arg) \
 	return dst; \
 } \
 \
-void \
+void CPUCALL \
 inst##_Eb(UINT8 *out) \
 { \
 	UINT32 src, dst; \
@@ -93,14 +86,14 @@ inst##_Eb(UINT8 *out) \
 	*out = (UINT8)dst; \
 } \
 \
-void \
+void CPUCALL \
 inst##_Eb_ext(UINT32 madr) \
 { \
 \
-	cpu_memory_access_va_RMW(CPU_INST_SEGREG_INDEX, madr, inst##1, 0); \
+	cpu_vmemory_RMW_b(CPU_INST_SEGREG_INDEX, madr, inst##1, 0); \
 } \
 \
-void \
+void CPUCALL \
 inst##_Ew(UINT16 *out) \
 { \
 	UINT32 src, dst; \
@@ -110,14 +103,14 @@ inst##_Ew(UINT16 *out) \
 	*out = (UINT16)dst; \
 } \
 \
-void \
+void CPUCALL \
 inst##_Ew_ext(UINT32 madr) \
 { \
 \
-	cpu_memory_access_va_RMW_w(CPU_INST_SEGREG_INDEX, madr, inst##2, 0); \
+	cpu_vmemory_RMW_w(CPU_INST_SEGREG_INDEX, madr, inst##2, 0); \
 } \
 \
-void \
+void CPUCALL \
 inst##_Ed(UINT32 *out) \
 { \
 	UINT32 src, dst; \
@@ -127,15 +120,15 @@ inst##_Ed(UINT32 *out) \
 	*out = dst; \
 } \
 \
-void \
+void CPUCALL \
 inst##_Ed_ext(UINT32 madr) \
 { \
 \
-	cpu_memory_access_va_RMW_d(CPU_INST_SEGREG_INDEX, madr, inst##4, 0); \
+	cpu_vmemory_RMW_d(CPU_INST_SEGREG_INDEX, madr, inst##4, 0); \
 } \
 \
 /* ExCL, ExIb */ \
-void \
+void CPUCALL \
 inst##_EbCL(UINT8 *out, UINT32 cl) \
 { \
 	UINT32 src, dst; \
@@ -145,14 +138,14 @@ inst##_EbCL(UINT8 *out, UINT32 cl) \
 	*out = (UINT8)dst; \
 } \
 \
-void \
+void CPUCALL \
 inst##_EbCL_ext(UINT32 madr, UINT32 cl) \
 { \
 \
-	cpu_memory_access_va_RMW(CPU_INST_SEGREG_INDEX, madr, inst##CL1, (void *)cl); \
+	cpu_vmemory_RMW_b(CPU_INST_SEGREG_INDEX, madr, inst##CL1, (void *)cl); \
 } \
 \
-void \
+void CPUCALL \
 inst##_EwCL(UINT16 *out, UINT32 cl) \
 { \
 	UINT32 src, dst; \
@@ -162,14 +155,14 @@ inst##_EwCL(UINT16 *out, UINT32 cl) \
 	*out = (UINT16)dst; \
 } \
 \
-void \
+void CPUCALL \
 inst##_EwCL_ext(UINT32 madr, UINT32 cl) \
 { \
 \
-	cpu_memory_access_va_RMW_w(CPU_INST_SEGREG_INDEX, madr, inst##CL2, (void *)cl); \
+	cpu_vmemory_RMW_w(CPU_INST_SEGREG_INDEX, madr, inst##CL2, (void *)cl); \
 } \
 \
-void \
+void CPUCALL \
 inst##_EdCL(UINT32 *out, UINT32 cl) \
 { \
 	UINT32 src, dst; \
@@ -179,11 +172,11 @@ inst##_EdCL(UINT32 *out, UINT32 cl) \
 	*out = dst; \
 } \
 \
-void \
+void CPUCALL \
 inst##_EdCL_ext(UINT32 madr, UINT32 cl) \
 { \
 \
-	cpu_memory_access_va_RMW_d(CPU_INST_SEGREG_INDEX, madr, inst##CL4, (void *)cl); \
+	cpu_vmemory_RMW_d(CPU_INST_SEGREG_INDEX, madr, inst##CL4, (void *)cl); \
 }
 
 /*
@@ -195,7 +188,7 @@ struct SHxD_arg {
 };
 
 #define	SHxD_INSTRUCTION(inst) \
-static UINT32 \
+static UINT32 CPUCALL \
 inst##2(UINT32 dst, void *arg) \
 { \
 	struct SHxD_arg *p = (struct SHxD_arg *)arg; \
@@ -204,7 +197,7 @@ inst##2(UINT32 dst, void *arg) \
 	WORD_##inst(dst, src, cl); \
 	return dst; \
 } \
-static UINT32 \
+static UINT32 CPUCALL \
 inst##4(UINT32 dst, void *arg) \
 { \
 	struct SHxD_arg *p = (struct SHxD_arg *)arg; \
@@ -233,7 +226,7 @@ inst##_EwGwIb(void) \
 		CPU_WORKCLOCK(7); \
 		madr = calc_ea_dst(op); \
 		GET_PCBYTE(arg.cl); \
-		cpu_memory_access_va_RMW_w(CPU_INST_SEGREG_INDEX, madr, inst##2, &arg); \
+		cpu_vmemory_RMW_w(CPU_INST_SEGREG_INDEX, madr, inst##2, &arg); \
 	} \
 } \
 \
@@ -256,7 +249,7 @@ inst##_EdGdIb(void) \
 		CPU_WORKCLOCK(7); \
 		madr = calc_ea_dst(op); \
 		GET_PCBYTE(arg.cl); \
-		cpu_memory_access_va_RMW_d(CPU_INST_SEGREG_INDEX, madr, inst##4, &arg); \
+		cpu_vmemory_RMW_d(CPU_INST_SEGREG_INDEX, madr, inst##4, &arg); \
 	} \
 } \
 \
@@ -278,7 +271,7 @@ inst##_EwGwCL(void) \
 	} else { \
 		CPU_WORKCLOCK(7); \
 		madr = calc_ea_dst(op); \
-		cpu_memory_access_va_RMW_w(CPU_INST_SEGREG_INDEX, madr, inst##2, (void *)&arg); \
+		cpu_vmemory_RMW_w(CPU_INST_SEGREG_INDEX, madr, inst##2, (void *)&arg); \
 	} \
 } \
 \
@@ -300,12 +293,12 @@ inst##_EdGdCL(void) \
 	} else { \
 		CPU_WORKCLOCK(7); \
 		madr = calc_ea_dst(op); \
-		cpu_memory_access_va_RMW_d(CPU_INST_SEGREG_INDEX, madr, inst##4, (void *)&arg); \
+		cpu_vmemory_RMW_d(CPU_INST_SEGREG_INDEX, madr, inst##4, (void *)&arg); \
 	} \
 }
 
 
-/* Pentium!!! - シフトカウント != 1の場合はOVは不変らすい */
+/* Pentium!!! - シフトカウント != 1の場合はOVは不変らすい */
 
 /*
  * SAR
@@ -888,8 +881,9 @@ do { \
 			CPU_OV = ((s) >> 31) ^ tmp; \
 		} \
 		while ((c)--) { \
-			tmp = (s) & 1; \
+			UINT32 tmp2 = (s) & 1; \
 			(s) = (tmp << 31) | ((s) >> 1); \
+			tmp = tmp2; \
 		} \
 		CPU_FLAGL |= tmp; \
 	} \
@@ -969,16 +963,16 @@ do { \
 			CPU_OV = ((s) + 0x40000000) & 0x80000000; \
 		} \
 		while ((c)--) { \
-			tmp = (s) & 0x80000000; \
+			UINT32 tmp2 = (s) & 0x80000000; \
 			(s) = ((s) << 1) | (tmp & 1); \
-			tmp >>= 31; \
+			tmp = tmp2 >> 31; \
 		} \
 		CPU_FLAGL |= tmp; \
 	} \
 	(d) = (s); \
 } while (/*CONSTCOND*/ 0)
 
-#if defined(IA32_CROSS_CHECK) && defined(__GNUC__) && (defined(i386) || defined(i386))
+#if defined(IA32_CROSS_CHECK) && defined(GCC_CPU_ARCH_IA32)
 
 #include "shift_rotatexc.mcr"
 
@@ -1033,7 +1027,7 @@ do { \
 
 #include	"shift_rotatexc_msc.mcr"
 
-#else	/* !(IA32_CROSS_CHECK && __GNUC__ && (i386) || __i386__)) */
+#else	/* !(IA32_CROSS_CHECK && GCC_CPU_ARCH_IA32 */
 
 #define	BYTE_SAR1(d, s)		_BYTE_SAR1(d, s)
 #define	WORD_SAR1(d, s)		_WORD_SAR1(d, s)
@@ -1082,6 +1076,6 @@ do { \
 #define	WORD_RCLCL(d, s, c)	_WORD_RCLCL(d, s, c)
 #define	DWORD_RCLCL(d, s, c)	_DWORD_RCLCL(d, s, c)
 
-#endif	/* IA32_CROSS_CHECK && __GNUC__ && (i386) || __i386__) */
+#endif	/* IA32_CROSS_CHECK && GCC_CPU_ARCH_IA32 */
 
 #endif	/* IA32_CPU_SHIFT_ROTATE_MCR__ */