--- np2/i386c/ia32/instructions/system_inst.c	2003/12/11 15:01:00	1.2
+++ np2/i386c/ia32/instructions/system_inst.c	2004/01/29 11:42:58	1.12
@@ -1,4 +1,4 @@
-/*	$Id: system_inst.c,v 1.2 2003/12/11 15:01:00 monaka Exp $	*/
+/*	$Id: system_inst.c,v 1.12 2004/01/29 11:42:58 monaka Exp $	*/
 
 /*
  * Copyright (c) 2003 NONAKA Kimihiro
@@ -35,33 +35,7 @@
 
 
 void
-LGDT16_Ms(DWORD op)
-{
-	DWORD madr;
-	DWORD base;
-	WORD limit;
-
-	if (op < 0xc0) {
-		if (!CPU_STAT_PM || !CPU_STAT_VM86 || CPU_STAT_CPL == 0) {
-			CPU_WORKCLOCK(11);
-			madr = get_ea(op);
-			limit = cpu_vmemoryread_w(CPU_INST_SEGREG_INDEX, madr);
-			base = cpu_vmemoryread_d(CPU_INST_SEGREG_INDEX, madr + 2);
-			base &= 0x00ffffff;
-
-			VERBOSE(("LGDT16_Ms: GDTR_BASE = 0x%08x, GDTR_LIMIT = 0x%04x", base, limit));
-
-			CPU_GDTR_BASE = base;
-			CPU_GDTR_LIMIT = limit;
-			return;
-		}
-		EXCEPTION(GP_EXCEPTION, 0);
-	}
-	EXCEPTION(UD_EXCEPTION, 0);
-}
-
-void
-LGDT32_Ms(DWORD op)
+LGDT_Ms(DWORD op)
 {
 	DWORD madr;
 	DWORD base;
@@ -73,20 +47,26 @@ LGDT32_Ms(DWORD op)
 			madr = get_ea(op);
 			limit = cpu_vmemoryread_w(CPU_INST_SEGREG_INDEX, madr);
 			base = cpu_vmemoryread_d(CPU_INST_SEGREG_INDEX, madr + 2);
+			if (!CPU_INST_OP32) {
+				base &= 0x00ffffff;
+			}
 
-			VERBOSE(("LGDT32_Ms: GDTR_BASE = 0x%08x, GDTR_LIMIT = 0x%04x", base, limit));
+#if defined(MORE_DEBUG)
+			gdtr_dump(base, limit);
+#endif
 
 			CPU_GDTR_BASE = base;
 			CPU_GDTR_LIMIT = limit;
 			return;
 		}
+		VERBOSE(("LGDT: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
 		EXCEPTION(GP_EXCEPTION, 0);
 	}
 	EXCEPTION(UD_EXCEPTION, 0);
 }
 
 void
-SGDT16_Ms(DWORD op)
+SGDT_Ms(DWORD op)
 {
 	DWORD madr;
 	DWORD base;
@@ -94,27 +74,11 @@ SGDT16_Ms(DWORD op)
 
 	if (op < 0xc0) {
 		CPU_WORKCLOCK(11);
-		base = CPU_GDTR_BASE & 0x00ffffff;
 		limit = CPU_GDTR_LIMIT;
-		madr = get_ea(op);
-		cpu_vmemorywrite_w(CPU_INST_SEGREG_INDEX, madr, limit);
-		cpu_vmemorywrite_d(CPU_INST_SEGREG_INDEX, madr + 2, base);
-		return;
-	}
-	EXCEPTION(UD_EXCEPTION, 0);
-}
-
-void
-SGDT32_Ms(DWORD op)
-{
-	DWORD madr;
-	DWORD base;
-	WORD limit;
-
-	if (op < 0xc0) {
-		CPU_WORKCLOCK(11);
 		base = CPU_GDTR_BASE;
-		limit = CPU_GDTR_LIMIT;
+		if (!CPU_INST_OP32) {
+			base &= 0x00ffffff;
+		}
 		madr = get_ea(op);
 		cpu_vmemorywrite_w(CPU_INST_SEGREG_INDEX, madr, limit);
 		cpu_vmemorywrite_d(CPU_INST_SEGREG_INDEX, madr + 2, base);
@@ -141,8 +105,10 @@ LLDT_Ew(DWORD op)
 			load_ldtr(src, GP_EXCEPTION);
 			return;
 		}
+		VERBOSE(("LLDT: CPL(%d) != 0", CPU_STAT_CPL));
 		EXCEPTION(GP_EXCEPTION, 0);
 	}
+	VERBOSE(("LLDT: VM86"));
 	EXCEPTION(UD_EXCEPTION, 0);
 }
 
@@ -150,30 +116,26 @@ void
 SLDT_Ew(DWORD op)
 {
 	DWORD madr;
+	WORD ldtr;
 
-	if (op >= 0xc0) {
-		CPU_WORKCLOCK(5);
-		*(reg16_b20[op]) = CPU_LDTR;
-	} else {
-		CPU_WORKCLOCK(11);
-		madr = calc_ea_dst(op);
-		cpu_vmemorywrite_w(CPU_INST_SEGREG_INDEX, madr, CPU_LDTR);
-	}
-}
-
-void
-SLDT_Ed(DWORD op)
-{
-	DWORD madr;
-
-	if (op >= 0xc0) {
-		CPU_WORKCLOCK(5);
-		*(reg32_b20[op]) = CPU_LDTR;
-	} else {
-		CPU_WORKCLOCK(11);
-		madr = calc_ea_dst(op);
-		cpu_vmemorywrite_d(CPU_INST_SEGREG_INDEX, madr, CPU_LDTR);
+	if (CPU_STAT_PM && !CPU_STAT_VM86) {
+		ldtr = CPU_LDTR;
+		if (op >= 0xc0) {
+			CPU_WORKCLOCK(5);
+			if (CPU_INST_OP32) {
+				*(reg32_b20[op]) = ldtr;
+			} else {
+				*(reg16_b20[op]) = ldtr;
+			}
+		} else {
+			CPU_WORKCLOCK(11);
+			madr = calc_ea_dst(op);
+			cpu_vmemorywrite_w(CPU_INST_SEGREG_INDEX, madr, ldtr);
+		}
+		return;
 	}
+	VERBOSE(("SLDT: VM86"));
+	EXCEPTION(UD_EXCEPTION, 0);
 }
 
 void
@@ -194,8 +156,10 @@ LTR_Ew(DWORD op)
 			load_tr(src);
 			return;
 		}
+		VERBOSE(("LTR: CPL(%d) != 0", CPU_STAT_CPL));
 		EXCEPTION(GP_EXCEPTION, 0);
 	}
+	VERBOSE(("LTR: VM86"));
 	EXCEPTION(UD_EXCEPTION, 0);
 }
 
@@ -203,92 +167,61 @@ void
 STR_Ew(DWORD op)
 {
 	DWORD madr;
+	WORD tr;
 
-	if (op >= 0xc0) {
-		CPU_WORKCLOCK(5);
-		*(reg16_b20[op]) = CPU_TR;
-	} else {
-		CPU_WORKCLOCK(11);
-		madr = calc_ea_dst(op);
-		cpu_vmemorywrite_w(CPU_INST_SEGREG_INDEX, madr, CPU_TR);
-	}
-}
-
-void
-STR_Ed(DWORD op)
-{
-	DWORD madr;
-
-	if (op >= 0xc0) {
-		CPU_WORKCLOCK(5);
-		*(reg32_b20[op]) = CPU_TR;
-	} else {
-		CPU_WORKCLOCK(11);
-		madr = calc_ea_dst(op);
-		cpu_vmemorywrite_d(CPU_INST_SEGREG_INDEX, madr, CPU_TR);
-	}
-}
-
-void
-LIDT16_Ms(DWORD op)
-{
-	DWORD madr;
-	DWORD base;
-	WORD limit;
-
-	if (op < 0xc0) {
-		CPU_WORKCLOCK(11);
-		madr = get_ea(op);
-		limit = cpu_vmemoryread_w(CPU_INST_SEGREG_INDEX, madr);
-		base = cpu_vmemoryread_d(CPU_INST_SEGREG_INDEX, madr + 2);
-		base &= 0x00ffffff;
-		CPU_IDTR_BASE = base;
-		CPU_IDTR_LIMIT = limit;
+	if (CPU_STAT_PM && !CPU_STAT_VM86) {
+		tr = CPU_TR;
+		if (op >= 0xc0) {
+			CPU_WORKCLOCK(5);
+			if (CPU_INST_OP32) {
+				*(reg32_b20[op]) = tr;
+			} else {
+				*(reg16_b20[op]) = tr;
+			}
+		} else {
+			CPU_WORKCLOCK(11);
+			madr = calc_ea_dst(op);
+			cpu_vmemorywrite_w(CPU_INST_SEGREG_INDEX, madr, tr);
+		}
 		return;
 	}
+	VERBOSE(("STR: VM86"));
 	EXCEPTION(UD_EXCEPTION, 0);
 }
 
 void
-LIDT32_Ms(DWORD op)
+LIDT_Ms(DWORD op)
 {
 	DWORD madr;
 	DWORD base;
 	WORD limit;
 
 	if (op < 0xc0) {
-		CPU_WORKCLOCK(11);
-		madr = get_ea(op);
-		limit = cpu_vmemoryread_w(CPU_INST_SEGREG_INDEX, madr);
-		base = cpu_vmemoryread_d(CPU_INST_SEGREG_INDEX, madr + 2);
-		CPU_IDTR_BASE = base;
-		CPU_IDTR_LIMIT = limit;
-		return;
-	}
-	EXCEPTION(UD_EXCEPTION, 0);
-}
+		if (!CPU_STAT_PM || !CPU_STAT_VM86 || CPU_STAT_CPL == 0) {
+			CPU_WORKCLOCK(11);
+			madr = get_ea(op);
+			limit = cpu_vmemoryread_w(CPU_INST_SEGREG_INDEX, madr);
+			base = cpu_vmemoryread_d(CPU_INST_SEGREG_INDEX, madr + 2);
+			if (!CPU_INST_OP32) {
+				base &= 0x00ffffff;
+			}
 
-void
-SIDT16_Ms(DWORD op)
-{
-	DWORD madr;
-	DWORD base;
-	WORD limit;
+#if defined(MORE_DEBUG)
+			idtr_dump(base, limit);
+#endif
 
-	if (op < 0xc0) {
-		CPU_WORKCLOCK(11);
-		base = CPU_IDTR_BASE & 0x00ffffff;
-		limit = CPU_IDTR_LIMIT;
-		madr = get_ea(op);
-		cpu_vmemorywrite_w(CPU_INST_SEGREG_INDEX, madr, limit);
-		cpu_vmemorywrite_d(CPU_INST_SEGREG_INDEX, madr + 2, base);
-		return;
+			CPU_IDTR_BASE = base;
+			CPU_IDTR_LIMIT = limit;
+			return;
+		}
+		VERBOSE(("LIDT: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
+		EXCEPTION(GP_EXCEPTION, 0);
 	}
 	EXCEPTION(UD_EXCEPTION, 0);
 }
 
 void
-SIDT32_Ms(DWORD op)
+SIDT_Ms(DWORD op)
 {
 	DWORD madr;
 	DWORD base;
@@ -296,8 +229,11 @@ SIDT32_Ms(DWORD op)
 
 	if (op < 0xc0) {
 		CPU_WORKCLOCK(11);
-		base = CPU_IDTR_BASE;
 		limit = CPU_IDTR_LIMIT;
+		base = CPU_IDTR_BASE;
+		if (!CPU_INST_OP32) {
+			base &= 0x00ffffff;
+		}
 		madr = get_ea(op);
 		cpu_vmemorywrite_w(CPU_INST_SEGREG_INDEX, madr, limit);
 		cpu_vmemorywrite_d(CPU_INST_SEGREG_INDEX, madr + 2, base);
@@ -317,11 +253,13 @@ MOV_CdRd(void)
 	GET_PCBYTE(op);
 	if (op >= 0xc0) {
 		if (CPU_STAT_PM && (CPU_STAT_VM86 || CPU_STAT_CPL != 0)) {
+			VERBOSE(("MOV_CdRd: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
 			EXCEPTION(GP_EXCEPTION, 0);
 		}
 
 		src = *(reg32_b20[op]);
 		idx = (op >> 3) & 7;
+
 		switch (idx) {
 		case 0: /* CR0 */
 			/*
@@ -354,7 +292,7 @@ MOV_CdRd(void)
 			src |= CPU_CR0_ET;	/* FPU present */
 #endif
 			CPU_CR0 = src;
-			VERBOSE(("cr0: 0x%08x -> 0x%08x", reg, CPU_CR0));
+			VERBOSE(("MOV_CdRd: %04x:%08x: cr0: 0x%08x <- 0x%08x(%s)", CPU_CS, CPU_PREV_EIP, reg, CPU_CR0, reg32_str[op & 7]));
 
 			if ((reg ^ CPU_CR0) & (CPU_CR0_PE|CPU_CR0_PG)) {
 				tlb_flush(FALSE);
@@ -381,7 +319,7 @@ MOV_CdRd(void)
 		case 2: /* CR2 */
 			reg = CPU_CR2;
 			CPU_CR2 = src;	/* page fault linear address */
-			VERBOSE(("cr2: 0x%08x -> 0x%08x", reg, CPU_CR2));
+			VERBOSE(("MOV_CdRd: %04x:%08x: cr2: 0x%08x <- 0x%08x(%s)", CPU_CS, CPU_PREV_EIP, reg, CPU_CR2, reg32_str[op & 7]));
 			break;
 
 		case 3: /* CR3 */
@@ -391,11 +329,11 @@ MOV_CdRd(void)
 			 * 3 = PWT (page level write throgh)
 			 */
 			reg = CPU_CR3;
-			CPU_CR3 = src & 0xfffff018;
-			VERBOSE(("cr3: 0x%08x -> 0x%08x", reg, CPU_CR3));
-			tlb_flush(FALSE);
+			set_CR3(src);
+			VERBOSE(("MOV_CdRd: %04x:%08x: cr3: 0x%08x <- 0x%08x(%s)", CPU_CS, CPU_PREV_EIP, reg, CPU_CR3, reg32_str[op & 7]));
 			break;
 
+#if CPU_FAMILY >= 5
 		case 4: /* CR4 */
 			/*
 			 * 10 = OSXMMEXCPT (support non masking exception by OS)
@@ -420,12 +358,13 @@ MOV_CdRd(void)
 
 			reg = CPU_CR4;
 			CPU_CR4 = src;
-			VERBOSE(("cr4: 0x%08x -> 0x%08x", reg, CPU_CR4));
+			VERBOSE(("MOV_CdRd: %04x:%08x: cr4: 0x%08x <- 0x%08x(%s)", CPU_CS, CPU_PREV_EIP, reg, CPU_CR4, reg32_str[op & 7]));
 
 			if ((reg ^ CPU_CR4) & (CPU_CR4_PSE|CPU_CR4_PGE|CPU_CR4_PAE)) {
 				tlb_flush(FALSE);
 			}
 			break;
+#endif	/* CPU_FAMILY >= 5 */
 
 		default:
 			ia32_panic("MOV_CdRd: CR reg index (%d)", idx);
@@ -442,15 +381,20 @@ MOV_RdCd(void)
 {
 	DWORD *out;
 	DWORD op;
+	int idx;
 
 	CPU_WORKCLOCK(11);
-	PREPART_EA_REG32P(op, out);
+	GET_PCBYTE(op);
 	if (op >= 0xc0) {
 		if (CPU_STAT_PM && (CPU_STAT_VM86 || CPU_STAT_CPL != 0)) {
+			VERBOSE(("MOV_CdRd: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
 			EXCEPTION(GP_EXCEPTION, 0);
 		}
 
-		switch (op & 7) {
+		out = reg32_b20[op];
+		idx = (op >> 3) & 7;
+
+		switch (idx) {
 		case 0:
 			*out = CPU_CR0;
 			break;
@@ -463,15 +407,18 @@ MOV_RdCd(void)
 			*out = CPU_CR3;
 			break;
 
+#if CPU_FAMILY >= 5
 		case 4:
 			*out = CPU_CR4;
 			break;
+#endif	/* CPU_FAMILY >= 5 */
 
 		default:
-			ia32_panic("MOV_RdCd: CR reg index (%d)", op & 7);
+			ia32_panic("MOV_RdCd: CR reg index (%d)", idx);
 			/*NOTREACHED*/
 			break;
 		}
+		VERBOSE(("MOV_RdCd: %04x:%08x: cr%d: 0x%08x -> %s", CPU_CS, CPU_PREV_EIP, idx, *out, reg32_str[op & 7]));
 		return;
 	}
 	EXCEPTION(UD_EXCEPTION, 0);
@@ -481,25 +428,28 @@ void
 LMSW_Ew(DWORD op)
 {
 	DWORD src, madr;
+	DWORD cr0;
 
-	if (CPU_STAT_PM && CPU_STAT_CPL != 0) {
-		EXCEPTION(GP_EXCEPTION, 0);
-	}
-
-	if (op >= 0xc0) {
-		CPU_WORKCLOCK(2);
-		src = *(reg16_b20[op]);
-	} else {
-		CPU_WORKCLOCK(3);
-		madr = calc_ea_dst(op);
-		src = cpu_vmemoryread_w(CPU_INST_SEGREG_INDEX, madr);
-	}
+	if (!CPU_STAT_PM || CPU_STAT_CPL == 0) {
+		if (op >= 0xc0) {
+			CPU_WORKCLOCK(2);
+			src = *(reg16_b20[op]);
+		} else {
+			CPU_WORKCLOCK(3);
+			madr = calc_ea_dst(op);
+			src = cpu_vmemoryread_w(CPU_INST_SEGREG_INDEX, madr);
+		}
 
-	CPU_CR0 &= ~0xfffffffe;	/* can't switch back from protected mode */
-	CPU_CR0 |= (src & 0xf);	/* TS, EM, MP, PE */
-	if ((src ^ CPU_CR0) & CPU_CR0_PE) {
-		change_pm(1);	/* switch to protected mode */
+		cr0 = CPU_CR0;
+		CPU_CR0 &= ~0xe; /* can't switch back from protected mode */
+		CPU_CR0 |= (src & 0xf);	/* TS, EM, MP, PE */
+		if (!(cr0 & CPU_CR0_PE) && (src & CPU_CR0_PE)) {
+			change_pm(1);	/* switch to protected mode */
+		}
+		return;
 	}
+	VERBOSE(("LMSW: CPL(%d) != 0", CPU_STAT_CPL));
+	EXCEPTION(GP_EXCEPTION, 0);
 }
 
 void
@@ -518,26 +468,12 @@ SMSW_Ew(DWORD op)
 }
 
 void
-SMSW_Ed(DWORD op)
-{
-	DWORD madr;
-
-	if (op >= 0xc0) {
-		CPU_WORKCLOCK(2);
-		*(reg32_b20[op]) = CPU_CR0;
-	} else {
-		CPU_WORKCLOCK(3);
-		madr = calc_ea_dst(op);
-		cpu_vmemorywrite_d(CPU_INST_SEGREG_INDEX, madr, CPU_CR0);
-	}
-}
-
-void
 CLTS(void)
 {
 
 	CPU_WORKCLOCK(2);
-	if (CPU_STAT_PM && CPU_STAT_CPL != 0) {
+	if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL != 0))) {
+		VERBOSE(("CLTS: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
 		EXCEPTION(GP_EXCEPTION, 0);
 	}
 	CPU_CR0 &= ~CPU_CR0_TS;
@@ -553,21 +489,30 @@ ARPL_EwGw(void)
 		if (op >= 0xc0) {
 			CPU_WORKCLOCK(2);
 			dst = *(reg16_b20[op]);
+			if ((dst & 3) < (src & 3)) {
+				CPU_FLAGL |= Z_FLAG;
+				dst &= ~3;
+				dst |= (src & 3);
+				*(reg16_b20[op]) = dst;
+			} else {
+				CPU_FLAGL &= ~Z_FLAG;
+			}
 		} else {
 			CPU_WORKCLOCK(3);
 			madr = calc_ea_dst(op);
 			dst = cpu_vmemoryread_w(CPU_INST_SEGREG_INDEX, madr);
-		}
-
-		if ((dst & 3) < (src & 3)) {
-			dst &= ~3;
-			dst |= (src & 3);
-			CPU_FLAGL |= Z_FLAG;
-		} else {
-			CPU_FLAGL &= ~Z_FLAG;
+			if ((dst & 3) < (src & 3)) {
+				CPU_FLAGL |= Z_FLAG;
+				dst &= ~3;
+				dst |= (src & 3);
+				cpu_vmemorywrite_w(CPU_INST_SEGREG_INDEX, madr, dst);
+			} else {
+				CPU_FLAGL &= ~Z_FLAG;
+			}
 		}
 		return;
 	}
+	VERBOSE(("ARPL: VM86"));
 	EXCEPTION(UD_EXCEPTION, 0);
 }
 
@@ -620,6 +565,7 @@ LAR_GwEw(void)
 		CPU_FLAGL |= Z_FLAG;
 		return;
 	}
+	VERBOSE(("LAR: VM86"));
 	EXCEPTION(UD_EXCEPTION, 0);
 }
 
@@ -669,6 +615,7 @@ LAR_GdEw(void)
 		CPU_FLAGL |= Z_FLAG;
 		return;
 	}
+	VERBOSE(("LAR: VM86"));
 	EXCEPTION(UD_EXCEPTION, 0);
 }
 
@@ -715,6 +662,7 @@ LSL_GwEw(void)
 		CPU_FLAGL |= Z_FLAG;
 		return;
 	}
+	VERBOSE(("LSL: VM86"));
 	EXCEPTION(UD_EXCEPTION, 0);
 }
 
@@ -761,6 +709,7 @@ LSL_GdEw(void)
 		CPU_FLAGL |= Z_FLAG;
 		return;
 	}
+	VERBOSE(("LSL: VM86"));
 	EXCEPTION(UD_EXCEPTION, 0);
 }
 
@@ -807,6 +756,7 @@ VERR_Ew(DWORD op)
 		CPU_FLAGL |= Z_FLAG;
 		return;
 	}
+	VERBOSE(("VERR: VM86"));
 	EXCEPTION(UD_EXCEPTION, 0);
 }
 
@@ -840,7 +790,7 @@ VERW_Ew(DWORD op)
 			return;
 		}
 		/* data segment is not writable */
-		if (sel.desc.u.seg.c && !sel.desc.u.seg.wr) {
+		if (!sel.desc.u.seg.wr) {
 			CPU_FLAGL &= ~Z_FLAG;
 			return;
 		}
@@ -852,6 +802,7 @@ VERW_Ew(DWORD op)
 		CPU_FLAGL |= Z_FLAG;
 		return;
 	}
+	VERBOSE(("VERW: VM86"));
 	EXCEPTION(UD_EXCEPTION, 0);
 }
 
@@ -875,6 +826,7 @@ INVD(void)
 
 	CPU_WORKCLOCK(11);
 	if (CPU_STAT_PM && (CPU_STAT_VM86 || CPU_STAT_CPL != 0)) {
+		VERBOSE(("INVD: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
 		EXCEPTION(GP_EXCEPTION, 0);
 	}
 	/* nothing to do */
@@ -886,6 +838,7 @@ WBINVD(void)
 
 	CPU_WORKCLOCK(11);
 	if (CPU_STAT_PM && (CPU_STAT_VM86 || CPU_STAT_CPL != 0)) {
+		VERBOSE(("WBINVD: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
 		EXCEPTION(GP_EXCEPTION, 0);
 	}
 	/* nothing to do */
@@ -897,6 +850,7 @@ INVLPG(DWORD op)
 	DWORD madr;
 
 	if (CPU_STAT_PM && (CPU_STAT_VM86 || CPU_STAT_CPL != 0)) {
+		VERBOSE(("INVLPG: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
 		EXCEPTION(GP_EXCEPTION, 0);
 	}
 
@@ -921,6 +875,7 @@ HLT(void)
 {
 
 	if (CPU_STAT_PM && CPU_STAT_CPL != 0) {
+		VERBOSE(("HLT: CPL(%d) != 0", CPU_STAT_CPL));
 		EXCEPTION(GP_EXCEPTION, 0);
 	}
 
@@ -938,28 +893,39 @@ RSM(void)
 void
 RDMSR(void)
 {
+	int idx;
 
-#if 1
-	EXCEPTION(UD_EXCEPTION, 0);
-#else
 	if (CPU_STAT_PM && (CPU_STAT_VM86 || CPU_STAT_CPL != 0)) {
+		VERBOSE(("RDMSR: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
 		EXCEPTION(GP_EXCEPTION, 0);
 	}
-#endif
+
+	idx = CPU_ECX;
+	switch (idx) {
+	default:
+		EXCEPTION(GP_EXCEPTION, 0);
+		break;
+	}
 }
 
 void
 WRMSR(void)
 {
+	int idx;
 
-#if 1
-	EXCEPTION(UD_EXCEPTION, 0);
-#else
 	if (CPU_STAT_PM && (CPU_STAT_VM86 || CPU_STAT_CPL != 0)) {
+		VERBOSE(("WRMSR: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
 		EXCEPTION(GP_EXCEPTION, 0);
-		/* MTRR への書き込み時 tlb_flush(FALSE) */
 	}
-#endif
+
+	idx = CPU_ECX;
+	switch (idx) {
+		/* MTRR への書き込み時 tlb_flush(FALSE); */
+
+	default:
+		EXCEPTION(GP_EXCEPTION, 0);
+		break;
+	}
 }
 
 void