--- np2/i386c/ia32/instructions/system_inst.c	2004/03/04 15:53:11	1.20
+++ np2/i386c/ia32/instructions/system_inst.c	2011/01/15 17:17:23	1.34
@@ -1,5 +1,3 @@
-/*	$Id: system_inst.c,v 1.20 2004/03/04 15:53:11 monaka Exp $	*/
-
 /*
  * Copyright (c) 2003 NONAKA Kimihiro
  * All rights reserved.
@@ -12,8 +10,6 @@
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
@@ -42,7 +38,7 @@ LGDT_Ms(UINT32 op)
 	UINT16 limit;
 
 	if (op < 0xc0) {
-		if (!CPU_STAT_PM || !CPU_STAT_VM86 || CPU_STAT_CPL == 0) {
+		if (!CPU_STAT_PM || (CPU_STAT_CPL == 0 && !CPU_STAT_VM86)) {
 			CPU_WORKCLOCK(11);
 			madr = calc_ea_dst(op);
 			limit = cpu_vmemoryread_w(CPU_INST_SEGREG_INDEX, madr);
@@ -90,7 +86,8 @@ SGDT_Ms(UINT32 op)
 void
 LLDT_Ew(UINT32 op)
 {
-	UINT32 src, madr;
+	UINT32 madr;
+	UINT16 src;
 
 	if (CPU_STAT_PM && !CPU_STAT_VM86) {
 		if (CPU_STAT_CPL == 0) {
@@ -102,13 +99,13 @@ LLDT_Ew(UINT32 op)
 				madr = calc_ea_dst(op);
 				src = cpu_vmemoryread_w(CPU_INST_SEGREG_INDEX, madr);
 			}
-			load_ldtr((UINT16)src, GP_EXCEPTION);
+			load_ldtr(src, GP_EXCEPTION);
 			return;
 		}
 		VERBOSE(("LLDT: CPL(%d) != 0", CPU_STAT_CPL));
 		EXCEPTION(GP_EXCEPTION, 0);
 	}
-	VERBOSE(("LLDT: VM86"));
+	VERBOSE(("LLDT: real-mode or VM86"));
 	EXCEPTION(UD_EXCEPTION, 0);
 }
 
@@ -134,14 +131,15 @@ SLDT_Ew(UINT32 op)
 		}
 		return;
 	}
-	VERBOSE(("SLDT: VM86"));
+	VERBOSE(("SLDT: real-mode or VM86"));
 	EXCEPTION(UD_EXCEPTION, 0);
 }
 
 void
 LTR_Ew(UINT32 op)
 {
-	UINT32 src, madr;
+	UINT32 madr;
+	UINT16 src;
 
 	if (CPU_STAT_PM && !CPU_STAT_VM86) {
 		if (CPU_STAT_CPL == 0) {
@@ -153,13 +151,13 @@ LTR_Ew(UINT32 op)
 				madr = calc_ea_dst(op);
 				src = cpu_vmemoryread_w(CPU_INST_SEGREG_INDEX, madr);
 			}
-			load_tr((UINT16)src);
+			load_tr(src);
 			return;
 		}
 		VERBOSE(("LTR: CPL(%d) != 0", CPU_STAT_CPL));
 		EXCEPTION(GP_EXCEPTION, 0);
 	}
-	VERBOSE(("LTR: VM86"));
+	VERBOSE(("LTR: real-mode or VM86"));
 	EXCEPTION(UD_EXCEPTION, 0);
 }
 
@@ -185,7 +183,7 @@ STR_Ew(UINT32 op)
 		}
 		return;
 	}
-	VERBOSE(("STR: VM86"));
+	VERBOSE(("STR: real-mode or VM86"));
 	EXCEPTION(UD_EXCEPTION, 0);
 }
 
@@ -197,7 +195,7 @@ LIDT_Ms(UINT32 op)
 	UINT16 limit;
 
 	if (op < 0xc0) {
-		if (!CPU_STAT_PM || !CPU_STAT_VM86 || CPU_STAT_CPL == 0) {
+		if (!CPU_STAT_PM || (CPU_STAT_CPL == 0 && !CPU_STAT_VM86)) {
 			CPU_WORKCLOCK(11);
 			madr = calc_ea_dst(op);
 			limit = cpu_vmemoryread_w(CPU_INST_SEGREG_INDEX, madr);
@@ -285,17 +283,18 @@ MOV_CdRd(void)
 			}
 
 			reg = CPU_CR0;
-			src &= 0xe005003f;
-#ifndef USE_FPU
-			src &= ~CPU_CR0_ET;	/* FPU not present */
-#else
+			src &= CPU_CR0_ALL;
+#if defined(USE_FPU)
 			src |= CPU_CR0_ET;	/* FPU present */
+#else
+			src |= CPU_CR0_EM | CPU_CR0_NE;
+			src &= ~(CPU_CR0_MP | CPU_CR0_ET);
 #endif
 			CPU_CR0 = src;
 			VERBOSE(("MOV_CdRd: %04x:%08x: cr0: 0x%08x <- 0x%08x(%s)", CPU_CS, CPU_PREV_EIP, reg, CPU_CR0, reg32_str[op & 7]));
 
 			if ((reg ^ CPU_CR0) & (CPU_CR0_PE|CPU_CR0_PG)) {
-				tlb_flush(FALSE);
+				tlb_flush(1);
 			}
 			if ((reg ^ CPU_CR0) & CPU_CR0_PE) {
 				if (CPU_CR0 & CPU_CR0_PE) {
@@ -331,11 +330,10 @@ MOV_CdRd(void)
 			 * 3 = PWT (page level write throgh)
 			 */
 			reg = CPU_CR3;
-			set_CR3(src);
+			set_cr3(src);
 			VERBOSE(("MOV_CdRd: %04x:%08x: cr3: 0x%08x <- 0x%08x(%s)", CPU_CS, CPU_PREV_EIP, reg, CPU_CR3, reg32_str[op & 7]));
 			break;
 
-#if CPU_FAMILY >= 5
 		case 4: /* CR4 */
 			/*
 			 * 10 = OSXMMEXCPT (support non masking exception by OS)
@@ -350,7 +348,11 @@ MOV_CdRd(void)
 			 * 1 = PVI (protected mode virtual interrupt)
 			 * 0 = VME (VM8086 mode extention)
 			 */
-			reg = 0;	/* allow */
+			reg = 0		/* allow bit */
+#if (CPU_FEATURES & CPU_FEATURE_PGE) == CPU_FEATURE_PGE
+			    | CPU_CR4_PGE
+#endif
+			;
 			if (src & ~reg) {
 				if (src & 0xfffffc00) {
 					EXCEPTION(GP_EXCEPTION, 0);
@@ -363,10 +365,9 @@ MOV_CdRd(void)
 			VERBOSE(("MOV_CdRd: %04x:%08x: cr4: 0x%08x <- 0x%08x(%s)", CPU_CS, CPU_PREV_EIP, reg, CPU_CR4, reg32_str[op & 7]));
 
 			if ((reg ^ CPU_CR4) & (CPU_CR4_PSE|CPU_CR4_PGE|CPU_CR4_PAE)) {
-				tlb_flush(FALSE);
+				tlb_flush(1);
 			}
 			break;
-#endif	/* CPU_FAMILY >= 5 */
 
 		default:
 			ia32_panic("MOV_CdRd: CR reg index (%d)", idx);
@@ -389,7 +390,7 @@ MOV_RdCd(void)
 	GET_PCBYTE(op);
 	if (op >= 0xc0) {
 		if (CPU_STAT_PM && (CPU_STAT_VM86 || CPU_STAT_CPL != 0)) {
-			VERBOSE(("MOV_CdRd: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
+			VERBOSE(("MOV_RdCd: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
 			EXCEPTION(GP_EXCEPTION, 0);
 		}
 
@@ -409,11 +410,9 @@ MOV_RdCd(void)
 			*out = CPU_CR3;
 			break;
 
-#if CPU_FAMILY >= 5
 		case 4:
 			*out = CPU_CR4;
 			break;
-#endif	/* CPU_FAMILY >= 5 */
 
 		default:
 			ia32_panic("MOV_RdCd: CR reg index (%d)", idx);
@@ -461,7 +460,11 @@ SMSW_Ew(UINT32 op)
 
 	if (op >= 0xc0) {
 		CPU_WORKCLOCK(2);
-		*(reg16_b20[op]) = (UINT16)CPU_CR0;
+		if (CPU_INST_OP32) {
+			*(reg32_b20[op]) = (UINT16)CPU_CR0;
+		} else {
+			*(reg16_b20[op]) = (UINT16)CPU_CR0;
+		}
 	} else {
 		CPU_WORKCLOCK(3);
 		madr = calc_ea_dst(op);
@@ -484,7 +487,8 @@ CLTS(void)
 void
 ARPL_EwGw(void)
 {
-	UINT32 op, src, dst, madr;
+	UINT32 op, madr;
+	UINT src, dst;
 
 	if (CPU_STAT_PM && !CPU_STAT_VM86) {
 		PREPART_EA_REG16(op, src);
@@ -514,7 +518,7 @@ ARPL_EwGw(void)
 		}
 		return;
 	}
-	VERBOSE(("ARPL: VM86"));
+	VERBOSE(("ARPL: real-mode or VM86"));
 	EXCEPTION(UD_EXCEPTION, 0);
 }
 
@@ -540,10 +544,11 @@ LAR_GwEw(void)
 			return;
 		}
 
-		if (sel.desc.s) {
+		if (!SEG_IS_SYSTEM(&sel.desc)) {
 			/* code or data segment */
-			if (!(sel.desc.u.seg.c && sel.desc.u.seg.ec)) {
-				/* not conforming code segment */
+			if ((SEG_IS_DATA(&sel.desc)
+			 || !SEG_IS_CONFORMING_CODE(&sel.desc))) {
+				/* data or non-conforming code segment */
 				if ((sel.desc.dpl < CPU_STAT_CPL)
 				 || (sel.desc.dpl < sel.rpl)) {
 					CPU_FLAGL &= ~Z_FLAG;
@@ -574,7 +579,7 @@ LAR_GwEw(void)
 		CPU_FLAGL |= Z_FLAG;
 		return;
 	}
-	VERBOSE(("LAR: VM86"));
+	VERBOSE(("LAR: real-mode or VM86"));
 	EXCEPTION(UD_EXCEPTION, 0);
 }
 
@@ -597,10 +602,11 @@ LAR_GdEw(void)
 			return;
 		}
 
-		if (sel.desc.s) {
+		if (!SEG_IS_SYSTEM(&sel.desc)) {
 			/* code or data segment */
-			if (!(sel.desc.u.seg.c && sel.desc.u.seg.ec)) {
-				/* not conforming code segment */
+			if ((SEG_IS_DATA(&sel.desc)
+			 || !SEG_IS_CONFORMING_CODE(&sel.desc))) {
+				/* data or non-conforming code segment */
 				if ((sel.desc.dpl < CPU_STAT_CPL)
 				 || (sel.desc.dpl < sel.rpl)) {
 					CPU_FLAGL &= ~Z_FLAG;
@@ -631,7 +637,7 @@ LAR_GdEw(void)
 		CPU_FLAGL |= Z_FLAG;
 		return;
 	}
-	VERBOSE(("LAR: VM86"));
+	VERBOSE(("LAR: real-mode or VM86"));
 	EXCEPTION(UD_EXCEPTION, 0);
 }
 
@@ -653,10 +659,11 @@ LSL_GwEw(void)
 			return;
 		}
 
-		if (sel.desc.s) {
+		if (!SEG_IS_SYSTEM(&sel.desc)) {
 			/* code or data segment */
-			if (!(sel.desc.u.seg.c && sel.desc.u.seg.ec)) {
-				/* not conforming code segment */
+			if ((SEG_IS_DATA(&sel.desc)
+			 || !SEG_IS_CONFORMING_CODE(&sel.desc))) {
+				/* data or non-conforming code segment */
 				if ((sel.desc.dpl < CPU_STAT_CPL)
 				 || (sel.desc.dpl < sel.rpl)) {
 					CPU_FLAGL &= ~Z_FLAG;
@@ -683,7 +690,7 @@ LSL_GwEw(void)
 		CPU_FLAGL |= Z_FLAG;
 		return;
 	}
-	VERBOSE(("LSL: VM86"));
+	VERBOSE(("LSL: real-mode or VM86"));
 	EXCEPTION(UD_EXCEPTION, 0);
 }
 
@@ -705,10 +712,11 @@ LSL_GdEw(void)
 			return;
 		}
 
-		if (sel.desc.s) {
+		if (!SEG_IS_SYSTEM(&sel.desc)) {
 			/* code or data segment */
-			if (!(sel.desc.u.seg.c && sel.desc.u.seg.ec)) {
-				/* not conforming code segment */
+			if ((SEG_IS_DATA(&sel.desc)
+			 || !SEG_IS_CONFORMING_CODE(&sel.desc))) {
+				/* data or non-conforming code segment */
 				if ((sel.desc.dpl < CPU_STAT_CPL)
 				 || (sel.desc.dpl < sel.rpl)) {
 					CPU_FLAGL &= ~Z_FLAG;
@@ -735,7 +743,7 @@ LSL_GdEw(void)
 		CPU_FLAGL |= Z_FLAG;
 		return;
 	}
-	VERBOSE(("LSL: VM86"));
+	VERBOSE(("LSL: real-mode or VM86"));
 	EXCEPTION(UD_EXCEPTION, 0);
 }
 
@@ -764,13 +772,14 @@ VERR_Ew(UINT32 op)
 		}
 
 		/* system segment */
-		if (!sel.desc.s) {
+		if (SEG_IS_SYSTEM(&sel.desc)) {
 			CPU_FLAGL &= ~Z_FLAG;
 			return;
 		}
-		/* not conforming code segment && (CPL > DPL || RPL > DPL) */
-		if (!(sel.desc.u.seg.c && sel.desc.u.seg.ec)) {
-			/* not conforming code segment */
+
+		/* data or non-conforming code segment */
+		if ((SEG_IS_DATA(&sel.desc)
+		 || !SEG_IS_CONFORMING_CODE(&sel.desc))) {
 			if ((sel.desc.dpl < CPU_STAT_CPL)
 			 || (sel.desc.dpl < sel.rpl)) {
 				CPU_FLAGL &= ~Z_FLAG;
@@ -778,7 +787,8 @@ VERR_Ew(UINT32 op)
 			}
 		}
 		/* code segment is not readable */
-		if (sel.desc.u.seg.c && !sel.desc.u.seg.wr) {
+		if (SEG_IS_CODE(&sel.desc)
+		 && !SEG_IS_READABLE_CODE(&sel.desc)) {
 			CPU_FLAGL &= ~Z_FLAG;
 			return;
 		}
@@ -786,7 +796,7 @@ VERR_Ew(UINT32 op)
 		CPU_FLAGL |= Z_FLAG;
 		return;
 	}
-	VERBOSE(("VERR: VM86"));
+	VERBOSE(("VERR: real-mode or VM86"));
 	EXCEPTION(UD_EXCEPTION, 0);
 }
 
@@ -815,12 +825,12 @@ VERW_Ew(UINT32 op)
 		}
 
 		/* system segment || code segment */
-		if (!sel.desc.s || sel.desc.u.seg.c) {
+		if (SEG_IS_SYSTEM(&sel.desc) || SEG_IS_CODE(&sel.desc)) {
 			CPU_FLAGL &= ~Z_FLAG;
 			return;
 		}
 		/* data segment is not writable */
-		if (!sel.desc.u.seg.wr) {
+		if (!SEG_IS_WRITABLE_DATA(&sel.desc)) {
 			CPU_FLAGL &= ~Z_FLAG;
 			return;
 		}
@@ -833,32 +843,122 @@ VERW_Ew(UINT32 op)
 		CPU_FLAGL |= Z_FLAG;
 		return;
 	}
-	VERBOSE(("VERW: VM86"));
+	VERBOSE(("VERW: real-mode or VM86"));
 	EXCEPTION(UD_EXCEPTION, 0);
 }
 
 void
 MOV_DdRd(void)
 {
+	UINT32 src;
 	UINT op;
+	int idx;
+#if defined(IA32_SUPPORT_DEBUG_REGISTER)
+	int i;
+#endif
 
+	CPU_WORKCLOCK(11);
 	GET_PCBYTE(op);
-	TRACEOUT(("mov dr, rd - %.4x:%.8x", CPU_CS, CPU_EIP));
-#if 0
-	ia32_panic("MOV_DdRd: not implemented yet!");
-#endif
+	if (op >= 0xc0) {
+		if (CPU_STAT_PM && (CPU_STAT_VM86 || CPU_STAT_CPL != 0)) {
+			VERBOSE(("MOV_DdRd: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
+			EXCEPTION(GP_EXCEPTION, 0);
+		}
+
+		if (CPU_DR7 & CPU_DR7_GD) {
+			CPU_DR6 |= CPU_DR6_BD;
+			CPU_DR7 &= ~CPU_DR7_GD;
+			EXCEPTION(DB_EXCEPTION, 0);
+		}
+
+		src = *(reg32_b20[op]);
+		idx = (op >> 3) & 7;
+
+		CPU_DR(idx) = src;
+		switch (idx) {
+		case 0:
+		case 1:
+		case 2:
+		case 3:
+			CPU_DR(idx) = src;
+			break;
+
+		case 6:
+			CPU_DR6 = src;
+			break;
+
+		case 7:
+			CPU_DR7 = src;
+			CPU_STAT_BP = 0;
+#if defined(IA32_SUPPORT_DEBUG_REGISTER)
+			for (i = 0; i < CPU_DEBUG_REG_INDEX_NUM; i++) {
+				if (CPU_DR7 & (CPU_DR7_L(i)|CPU_DR7_G(i))) {
+					CPU_STAT_BP |= (1 << i);
+				}
+			}
+#endif	/* IA32_SUPPORT_DEBUG_REGISTER */
+			break;
+
+		default:
+			ia32_panic("MOV_DdRd: DR reg index (%d)", idx);
+			/*NOTREACHED*/
+			break;
+		}
+
+		return;
+	}
+	EXCEPTION(UD_EXCEPTION, 0);
 }
 
 void
 MOV_RdDd(void)
 {
+	UINT32 *out;
 	UINT op;
+	int idx;
 
+	CPU_WORKCLOCK(11);
 	GET_PCBYTE(op);
-	TRACEOUT(("mov rd, dr - %.4x:%.8x", CPU_CS, CPU_EIP));
-#if 0
-	ia32_panic("MOV_DdRd: not implemented yet!");
-#endif
+	if (op >= 0xc0) {
+		if (CPU_STAT_PM && (CPU_STAT_VM86 || CPU_STAT_CPL != 0)) {
+			VERBOSE(("MOV_RdDd: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
+			EXCEPTION(GP_EXCEPTION, 0);
+		}
+
+		if (CPU_DR7 & CPU_DR7_GD) {
+			CPU_DR6 |= CPU_DR6_BD;
+			CPU_DR7 &= ~CPU_DR7_GD;
+			EXCEPTION(DB_EXCEPTION, 0);
+		}
+
+		out = reg32_b20[op];
+		idx = (op >> 3) & 7;
+
+		switch (idx) {
+		case 0:
+		case 1:
+		case 2:
+		case 3:
+			*out = CPU_DR(idx);
+			break;
+
+		case 4:
+		case 6:
+			*out = (CPU_DR6 & 0x0000f00f) | 0xffff0ff0;
+			break;
+
+		case 7:
+			*out = CPU_DR7;
+			break;
+
+		default:
+			ia32_panic("MOV_RdDd: DR reg index (%d)", idx);
+			/*NOTREACHED*/
+			break;
+		}
+		return;
+	}
+	EXCEPTION(UD_EXCEPTION, 0);
 }
 
 void
@@ -870,7 +970,6 @@ INVD(void)
 		VERBOSE(("INVD: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
 		EXCEPTION(GP_EXCEPTION, 0);
 	}
-	/* nothing to do */
 }
 
 void
@@ -882,16 +981,14 @@ WBINVD(void)
 		VERBOSE(("WBINVD: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
 		EXCEPTION(GP_EXCEPTION, 0);
 	}
-	/* nothing to do */
 }
 
 void
 INVLPG(UINT32 op)
 {
-	descriptor_t *sd;
+	descriptor_t *sdp;
 	UINT32 madr;
 	int idx;
-	int exc;
 
 	if (CPU_STAT_PM && (CPU_STAT_VM86 || CPU_STAT_CPL != 0)) {
 		VERBOSE(("INVLPG: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
@@ -903,41 +1000,29 @@ INVLPG(UINT32 op)
 		madr = calc_ea_dst(op);
 
 		idx = CPU_INST_SEGREG_INDEX;
-		sd = &CPU_STAT_SREG(idx);
-		if (!sd->valid) {
-			exc = GP_EXCEPTION;
-			goto err;
+		sdp = &CPU_STAT_SREG(idx);
+		if (!SEG_IS_VALID(sdp)) {
+			EXCEPTION(GP_EXCEPTION, 0);
 		}
-		switch (sd->type) {
+		switch (sdp->type) {
 		case 4: case 5: case 6: case 7:
-			if (madr <= sd->u.seg.limit) {
-				if (idx == CPU_SS_INDEX)
-					exc = SS_EXCEPTION;
-				else
-					exc = GP_EXCEPTION;
-				goto err;
+			if (madr <= sdp->u.seg.limit) {
+				EXCEPTION((idx == CPU_SS_INDEX) ?
+				    SS_EXCEPTION: GP_EXCEPTION, 0);
 			}
 			break;
 
 		default:
-			if (madr > sd->u.seg.limit) {
-				if (idx == CPU_SS_INDEX)
-					exc = SS_EXCEPTION;
-				else
-					exc = GP_EXCEPTION;
-				goto err;
+			if (madr > sdp->u.seg.limit) {
+				EXCEPTION((idx == CPU_SS_INDEX) ?
+				    SS_EXCEPTION: GP_EXCEPTION, 0);
 			}
 			break;
 		}
-		tlb_flush_page(sd->u.seg.segbase + madr);
+		tlb_flush_page(sdp->u.seg.segbase + madr);
+		return;
 	}
-	return;
-
-err:
-#if 0	/* XXX */
-	EXCEPTION(exc, 0);
-#endif
-	return;
+	EXCEPTION(UD_EXCEPTION, 0);
 }
 
 void
@@ -957,7 +1042,7 @@ HLT(void)
 	}
 
 	CPU_HALT();
-	CPU_EIP--;
+	CPU_EIP = CPU_PREV_EIP;
 	CPU_STAT_HLT = 1;
 }
 
@@ -998,7 +1083,7 @@ WRMSR(void)
 
 	idx = CPU_ECX;
 	switch (idx) {
-		/* MTRR への書き込み時 tlb_flush(FALSE); */
+		/* MTRR への書き込み時 tlb_flush(1); */
 
 	default:
 		EXCEPTION(GP_EXCEPTION, 0);