--- np2/i386c/ia32/instructions/system_inst.c	2004/03/04 15:20:13	1.19
+++ np2/i386c/ia32/instructions/system_inst.c	2004/03/07 04:09:27	1.21
@@ -1,4 +1,4 @@
-/*	$Id: system_inst.c,v 1.19 2004/03/04 15:20:13 yui Exp $	*/
+/*	$Id: system_inst.c,v 1.21 2004/03/07 04:09:27 yui Exp $	*/
 
 /*
  * Copyright (c) 2003 NONAKA Kimihiro
@@ -389,7 +389,7 @@ MOV_RdCd(void)
 	GET_PCBYTE(op);
 	if (op >= 0xc0) {
 		if (CPU_STAT_PM && (CPU_STAT_VM86 || CPU_STAT_CPL != 0)) {
-			VERBOSE(("MOV_CdRd: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
+			VERBOSE(("MOV_RdCd: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
 			EXCEPTION(GP_EXCEPTION, 0);
 		}
 
@@ -840,21 +840,59 @@ VERW_Ew(UINT32 op)
 void
 MOV_DdRd(void)
 {
-	UINT	op;
+#if 1
+	UINT32 op;
+	UINT32 src;
+	int idx;
 
+	CPU_WORKCLOCK(11);
 	GET_PCBYTE(op);
-	TRACEOUT(("mov dr, rd - %.4x:%.8x", CPU_CS, CPU_EIP));
-//	ia32_panic("MOV_DdRd: not implemented yet!");
+	if (op >= 0xc0) {
+		if (CPU_STAT_PM && (CPU_STAT_VM86 || CPU_STAT_CPL != 0)) {
+			TRACEOUT(("MOV_DdRd: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
+			EXCEPTION(GP_EXCEPTION, 0);
+		}
+
+		src = *(reg32_b20[op]);
+		idx = (op >> 3) & 7;
+		CPU_STATSAVE.cpu_regs.dr[idx] = src;
+
+		TRACEOUT(("MOV_DdRd: %04x:%08x: dr%d: 0x%08x <- %s", CPU_CS, CPU_PREV_EIP, idx, src, reg32_str[op & 7]));
+		return;
+	}
+	EXCEPTION(UD_EXCEPTION, 0);
+#else
+	ia32_panic("MOV_DdRd: not implemented yet!");
+#endif
 }
 
 void
 MOV_RdDd(void)
 {
-	UINT	op;
+#if 1
+	UINT32 *out;
+	UINT32 op;
+	int idx;
 
+	CPU_WORKCLOCK(11);
 	GET_PCBYTE(op);
-	TRACEOUT(("mov rd, dr - %.4x:%.8x", CPU_CS, CPU_EIP));
-//	ia32_panic("MOV_DdRd: not implemented yet!");
+	if (op >= 0xc0) {
+		if (CPU_STAT_PM && (CPU_STAT_VM86 || CPU_STAT_CPL != 0)) {
+			TRACEOUT(("MOV_RdDd: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
+			EXCEPTION(GP_EXCEPTION, 0);
+		}
+
+		out = reg32_b20[op];
+		idx = (op >> 3) & 7;
+		*out = CPU_STATSAVE.cpu_regs.dr[idx];
+
+		TRACEOUT(("MOV_RdDd: %04x:%08x: dr%d: 0x%08x -> %s", CPU_CS, CPU_PREV_EIP, idx, *out, reg32_str[op & 7]));
+		return;
+	}
+	EXCEPTION(UD_EXCEPTION, 0);
+#else
+	ia32_panic("MOV_DdRd: not implemented yet!");
+#endif
 }
 
 void
@@ -884,7 +922,10 @@ WBINVD(void)
 void
 INVLPG(UINT32 op)
 {
+	descriptor_t *sd;
 	UINT32 madr;
+	int idx;
+	int exc;
 
 	if (CPU_STAT_PM && (CPU_STAT_VM86 || CPU_STAT_CPL != 0)) {
 		VERBOSE(("INVLPG: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
@@ -894,10 +935,43 @@ INVLPG(UINT32 op)
 	if (op < 0xc0) {
 		CPU_WORKCLOCK(11);
 		madr = calc_ea_dst(op);
-		tlb_flush_page(madr);
-		return;
+
+		idx = CPU_INST_SEGREG_INDEX;
+		sd = &CPU_STAT_SREG(idx);
+		if (!sd->valid) {
+			exc = GP_EXCEPTION;
+			goto err;
+		}
+		switch (sd->type) {
+		case 4: case 5: case 6: case 7:
+			if (madr <= sd->u.seg.limit) {
+				if (idx == CPU_SS_INDEX)
+					exc = SS_EXCEPTION;
+				else
+					exc = GP_EXCEPTION;
+				goto err;
+			}
+			break;
+
+		default:
+			if (madr > sd->u.seg.limit) {
+				if (idx == CPU_SS_INDEX)
+					exc = SS_EXCEPTION;
+				else
+					exc = GP_EXCEPTION;
+				goto err;
+			}
+			break;
+		}
+		tlb_flush_page(sd->u.seg.segbase + madr);
 	}
-	EXCEPTION(UD_EXCEPTION, 0);
+	return;
+
+err:
+#if 0	/* XXX */
+	EXCEPTION(exc, 0);
+#endif
+	return;
 }
 
 void