--- np2/i386c/ia32/instructions/system_inst.c	2004/03/04 15:53:11	1.20
+++ np2/i386c/ia32/instructions/system_inst.c	2004/03/09 14:14:05	1.23
@@ -1,4 +1,4 @@
-/*	$Id: system_inst.c,v 1.20 2004/03/04 15:53:11 monaka Exp $	*/
+/*	$Id: system_inst.c,v 1.23 2004/03/09 14:14:05 monaka Exp $	*/
 
 /*
  * Copyright (c) 2003 NONAKA Kimihiro
@@ -389,7 +389,7 @@ MOV_RdCd(void)
 	GET_PCBYTE(op);
 	if (op >= 0xc0) {
 		if (CPU_STAT_PM && (CPU_STAT_VM86 || CPU_STAT_CPL != 0)) {
-			VERBOSE(("MOV_CdRd: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
+			VERBOSE(("MOV_RdCd: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
 			EXCEPTION(GP_EXCEPTION, 0);
 		}
 
@@ -484,7 +484,8 @@ CLTS(void)
 void
 ARPL_EwGw(void)
 {
-	UINT32 op, src, dst, madr;
+	UINT32 op, src, madr;
+	UINT16 dst;
 
 	if (CPU_STAT_PM && !CPU_STAT_VM86) {
 		PREPART_EA_REG16(op, src);
@@ -495,7 +496,7 @@ ARPL_EwGw(void)
 				CPU_FLAGL |= Z_FLAG;
 				dst &= ~3;
 				dst |= (src & 3);
-				*(reg16_b20[op]) = (UINT16)dst;
+				*(reg16_b20[op]) = dst;
 			} else {
 				CPU_FLAGL &= ~Z_FLAG;
 			}
@@ -507,7 +508,7 @@ ARPL_EwGw(void)
 				CPU_FLAGL |= Z_FLAG;
 				dst &= ~3;
 				dst |= (src & 3);
-				cpu_vmemorywrite_w(CPU_INST_SEGREG_INDEX, madr, (UINT16)dst);
+				cpu_vmemorywrite_w(CPU_INST_SEGREG_INDEX, madr, dst);
 			} else {
 				CPU_FLAGL &= ~Z_FLAG;
 			}
@@ -840,25 +841,140 @@ VERW_Ew(UINT32 op)
 void
 MOV_DdRd(void)
 {
+	UINT32 src;
 	UINT op;
+	int idx;
+	int i;
 
+	CPU_WORKCLOCK(11);
 	GET_PCBYTE(op);
-	TRACEOUT(("mov dr, rd - %.4x:%.8x", CPU_CS, CPU_EIP));
-#if 0
-	ia32_panic("MOV_DdRd: not implemented yet!");
+	if (op >= 0xc0) {
+		if (CPU_STAT_PM && (CPU_STAT_VM86 || CPU_STAT_CPL != 0)) {
+			VERBOSE(("MOV_DdRd: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
+			EXCEPTION(GP_EXCEPTION, 0);
+		}
+
+		if (CPU_DR7 & CPU_DR7_GD) {
+			CPU_DR6 |= CPU_DR6_BD;
+			CPU_DR7 &= ~CPU_DR7_GD;
+			EXCEPTION(DB_EXCEPTION, 0);
+		}
+
+		src = *(reg32_b20[op]);
+		idx = (op >> 3) & 7;
+
+		CPU_DR(idx) = src;
+		switch (idx) {
+		case 0:
+		case 1:
+		case 2:
+		case 3:
+			CPU_DR(idx) = src;
+			break;
+
+#if CPU_FAMILY >= 5
+		case 4:
+			if (CPU_CR4 & CPU_CR4_DE) {
+				EXCEPTION(UD_EXCEPTION, 0);
+			}
+#endif
+		case 6:
+			CPU_DR6 = src;
+			break;
+
+#if CPU_FAMILY >= 5
+		case 5:
+			if (CPU_CR4 & CPU_CR4_DE) {
+				EXCEPTION(UD_EXCEPTION, 0);
+			}
 #endif
+		case 7:
+			CPU_DR7 = src;
+			CPU_STAT_BP = 0;
+#if defined(IA32_SUPPORT_DEBUG_REGISTER)
+			for (i = 0; i < CPU_DEBUG_REG_INDEX_NUM; i++) {
+				if (CPU_DR7 & (CPU_DR7_L(i)|CPU_DR7_G(i))) {
+					CPU_STAT_BP |= (1 << i);
+				}
+			}
+#endif	/* IA32_SUPPORT_DEBUG_REGISTER */
+			break;
+
+		default:
+			ia32_panic("MOV_DdRd: DR reg index (%d)", idx);
+			/*NOTREACHED*/
+			break;
+		}
+
+		return;
+	}
+	EXCEPTION(UD_EXCEPTION, 0);
 }
 
 void
 MOV_RdDd(void)
 {
+	UINT32 *out;
 	UINT op;
+	int idx;
 
+	CPU_WORKCLOCK(11);
 	GET_PCBYTE(op);
-	TRACEOUT(("mov rd, dr - %.4x:%.8x", CPU_CS, CPU_EIP));
-#if 0
-	ia32_panic("MOV_DdRd: not implemented yet!");
+	if (op >= 0xc0) {
+		if (CPU_STAT_PM && (CPU_STAT_VM86 || CPU_STAT_CPL != 0)) {
+			VERBOSE(("MOV_RdDd: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
+			EXCEPTION(GP_EXCEPTION, 0);
+		}
+
+		if (CPU_DR7 & CPU_DR7_GD) {
+			CPU_DR6 |= CPU_DR6_BD;
+			CPU_DR7 &= ~CPU_DR7_GD;
+			EXCEPTION(DB_EXCEPTION, 0);
+		}
+
+		out = reg32_b20[op];
+		idx = (op >> 3) & 7;
+
+		switch (idx) {
+		case 0:
+		case 1:
+		case 2:
+		case 3:
+			*out = CPU_DR(idx);
+			break;
+
+		case 4:
+#if CPU_FAMILY >= 5
+			if (CPU_CR4 & CPU_CR4_DE) {
+				EXCEPTION(UD_EXCEPTION, 0);
+			}
+#endif
+		case 6:
+#if CPU_FAMILY == 4
+			*out = (CPU_DR6 & 0x0000f00f) | 0xffff0ff0;
+#elif CPU_FAMILY >= 5
+			*out = (CPU_DR6 & 0x0000e00f) | 0xffff0ff0;
 #endif
+			break;
+
+#if CPU_FAMILY >= 5
+		case 5:
+			if (CPU_CR4 & CPU_CR4_DE) {
+				EXCEPTION(UD_EXCEPTION, 0);
+			}
+#endif
+		case 7:
+			*out = CPU_DR7;
+			break;
+
+		default:
+			ia32_panic("MOV_RdDd: DR reg index (%d)", idx);
+			/*NOTREACHED*/
+			break;
+		}
+		return;
+	}
+	EXCEPTION(UD_EXCEPTION, 0);
 }
 
 void
@@ -870,7 +986,8 @@ INVD(void)
 		VERBOSE(("INVD: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
 		EXCEPTION(GP_EXCEPTION, 0);
 	}
-	/* nothing to do */
+
+	tlb_flush(TRUE);
 }
 
 void
@@ -882,7 +999,8 @@ WBINVD(void)
 		VERBOSE(("WBINVD: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
 		EXCEPTION(GP_EXCEPTION, 0);
 	}
-	/* nothing to do */
+
+	tlb_flush(TRUE);
 }
 
 void
@@ -930,14 +1048,11 @@ INVLPG(UINT32 op)
 			break;
 		}
 		tlb_flush_page(sd->u.seg.segbase + madr);
+		return;
 	}
-	return;
-
+	exc = UD_EXCEPTION;
 err:
-#if 0	/* XXX */
 	EXCEPTION(exc, 0);
-#endif
-	return;
 }
 
 void
@@ -958,6 +1073,9 @@ HLT(void)
 
 	CPU_HALT();
 	CPU_EIP--;
+#if defined(IA32_SUPPORT_PREFETCH_QUEUE)
+	CPU_PREFETCHQ_REMAIN++;
+#endif
 	CPU_STAT_HLT = 1;
 }