--- np2/i386c/ia32/instructions/system_inst.c	2004/03/08 12:56:22	1.22
+++ np2/i386c/ia32/instructions/system_inst.c	2004/03/12 15:10:38	1.25
@@ -1,4 +1,4 @@
-/*	$Id: system_inst.c,v 1.22 2004/03/08 12:56:22 monaka Exp $	*/
+/*	$Id: system_inst.c,v 1.25 2004/03/12 15:10:38 monaka Exp $	*/
 
 /*
  * Copyright (c) 2003 NONAKA Kimihiro
@@ -90,7 +90,8 @@ SGDT_Ms(UINT32 op)
 void
 LLDT_Ew(UINT32 op)
 {
-	UINT32 src, madr;
+	UINT32 madr;
+	UINT16 src;
 
 	if (CPU_STAT_PM && !CPU_STAT_VM86) {
 		if (CPU_STAT_CPL == 0) {
@@ -102,7 +103,7 @@ LLDT_Ew(UINT32 op)
 				madr = calc_ea_dst(op);
 				src = cpu_vmemoryread_w(CPU_INST_SEGREG_INDEX, madr);
 			}
-			load_ldtr((UINT16)src, GP_EXCEPTION);
+			load_ldtr(src, GP_EXCEPTION);
 			return;
 		}
 		VERBOSE(("LLDT: CPL(%d) != 0", CPU_STAT_CPL));
@@ -287,7 +288,8 @@ MOV_CdRd(void)
 			reg = CPU_CR0;
 			src &= 0xe005003f;
 #ifndef USE_FPU
-			src &= ~CPU_CR0_ET;	/* FPU not present */
+			src |= CPU_CR0_EM | CPU_CR0_NE;
+			src &= ~(CPU_CR0_MP | CPU_CR0_ET);
 #else
 			src |= CPU_CR0_ET;	/* FPU present */
 #endif
@@ -484,7 +486,8 @@ CLTS(void)
 void
 ARPL_EwGw(void)
 {
-	UINT32 op, src, dst, madr;
+	UINT32 op, src, madr;
+	UINT16 dst;
 
 	if (CPU_STAT_PM && !CPU_STAT_VM86) {
 		PREPART_EA_REG16(op, src);
@@ -495,7 +498,7 @@ ARPL_EwGw(void)
 				CPU_FLAGL |= Z_FLAG;
 				dst &= ~3;
 				dst |= (src & 3);
-				*(reg16_b20[op]) = (UINT16)dst;
+				*(reg16_b20[op]) = dst;
 			} else {
 				CPU_FLAGL &= ~Z_FLAG;
 			}
@@ -507,7 +510,7 @@ ARPL_EwGw(void)
 				CPU_FLAGL |= Z_FLAG;
 				dst &= ~3;
 				dst |= (src & 3);
-				cpu_vmemorywrite_w(CPU_INST_SEGREG_INDEX, madr, (UINT16)dst);
+				cpu_vmemorywrite_w(CPU_INST_SEGREG_INDEX, madr, dst);
 			} else {
 				CPU_FLAGL &= ~Z_FLAG;
 			}
@@ -985,7 +988,8 @@ INVD(void)
 		VERBOSE(("INVD: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
 		EXCEPTION(GP_EXCEPTION, 0);
 	}
-	/* nothing to do */
+
+	tlb_flush(TRUE);
 }
 
 void
@@ -997,7 +1001,8 @@ WBINVD(void)
 		VERBOSE(("WBINVD: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
 		EXCEPTION(GP_EXCEPTION, 0);
 	}
-	/* nothing to do */
+
+	tlb_flush(TRUE);
 }
 
 void
@@ -1045,14 +1050,11 @@ INVLPG(UINT32 op)
 			break;
 		}
 		tlb_flush_page(sd->u.seg.segbase + madr);
+		return;
 	}
-	return;
-
+	exc = UD_EXCEPTION;
 err:
-#if 0	/* XXX */
 	EXCEPTION(exc, 0);
-#endif
-	return;
 }
 
 void