--- np2/i386c/ia32/instructions/system_inst.c	2004/02/19 03:04:02	1.17
+++ np2/i386c/ia32/instructions/system_inst.c	2004/03/23 15:29:34	1.27
@@ -1,4 +1,4 @@
-/*	$Id: system_inst.c,v 1.17 2004/02/19 03:04:02 yui Exp $	*/
+/*	$Id: system_inst.c,v 1.27 2004/03/23 15:29:34 monaka Exp $	*/
 
 /*
  * Copyright (c) 2003 NONAKA Kimihiro
@@ -35,11 +35,11 @@
 
 
 void
-LGDT_Ms(DWORD op)
+LGDT_Ms(UINT32 op)
 {
-	DWORD madr;
-	DWORD base;
-	WORD limit;
+	UINT32 madr;
+	UINT32 base;
+	UINT16 limit;
 
 	if (op < 0xc0) {
 		if (!CPU_STAT_PM || !CPU_STAT_VM86 || CPU_STAT_CPL == 0) {
@@ -66,11 +66,11 @@ LGDT_Ms(DWORD op)
 }
 
 void
-SGDT_Ms(DWORD op)
+SGDT_Ms(UINT32 op)
 {
-	DWORD madr;
-	DWORD base;
-	WORD limit;
+	UINT32 madr;
+	UINT32 base;
+	UINT16 limit;
 
 	if (op < 0xc0) {
 		CPU_WORKCLOCK(11);
@@ -88,9 +88,10 @@ SGDT_Ms(DWORD op)
 }
 
 void
-LLDT_Ew(DWORD op)
+LLDT_Ew(UINT32 op)
 {
-	DWORD src, madr;
+	UINT32 madr;
+	UINT16 src;
 
 	if (CPU_STAT_PM && !CPU_STAT_VM86) {
 		if (CPU_STAT_CPL == 0) {
@@ -102,7 +103,7 @@ LLDT_Ew(DWORD op)
 				madr = calc_ea_dst(op);
 				src = cpu_vmemoryread_w(CPU_INST_SEGREG_INDEX, madr);
 			}
-			load_ldtr((WORD)src, GP_EXCEPTION);
+			load_ldtr(src, GP_EXCEPTION);
 			return;
 		}
 		VERBOSE(("LLDT: CPL(%d) != 0", CPU_STAT_CPL));
@@ -113,10 +114,10 @@ LLDT_Ew(DWORD op)
 }
 
 void
-SLDT_Ew(DWORD op)
+SLDT_Ew(UINT32 op)
 {
-	DWORD madr;
-	WORD ldtr;
+	UINT32 madr;
+	UINT16 ldtr;
 
 	if (CPU_STAT_PM && !CPU_STAT_VM86) {
 		ldtr = CPU_LDTR;
@@ -139,9 +140,10 @@ SLDT_Ew(DWORD op)
 }
 
 void
-LTR_Ew(DWORD op)
+LTR_Ew(UINT32 op)
 {
-	DWORD src, madr;
+	UINT32 madr;
+	UINT16 src;
 
 	if (CPU_STAT_PM && !CPU_STAT_VM86) {
 		if (CPU_STAT_CPL == 0) {
@@ -153,7 +155,7 @@ LTR_Ew(DWORD op)
 				madr = calc_ea_dst(op);
 				src = cpu_vmemoryread_w(CPU_INST_SEGREG_INDEX, madr);
 			}
-			load_tr((WORD)src);
+			load_tr(src);
 			return;
 		}
 		VERBOSE(("LTR: CPL(%d) != 0", CPU_STAT_CPL));
@@ -164,10 +166,10 @@ LTR_Ew(DWORD op)
 }
 
 void
-STR_Ew(DWORD op)
+STR_Ew(UINT32 op)
 {
-	DWORD madr;
-	WORD tr;
+	UINT32 madr;
+	UINT16 tr;
 
 	if (CPU_STAT_PM && !CPU_STAT_VM86) {
 		tr = CPU_TR;
@@ -190,11 +192,11 @@ STR_Ew(DWORD op)
 }
 
 void
-LIDT_Ms(DWORD op)
+LIDT_Ms(UINT32 op)
 {
-	DWORD madr;
-	DWORD base;
-	WORD limit;
+	UINT32 madr;
+	UINT32 base;
+	UINT16 limit;
 
 	if (op < 0xc0) {
 		if (!CPU_STAT_PM || !CPU_STAT_VM86 || CPU_STAT_CPL == 0) {
@@ -221,11 +223,11 @@ LIDT_Ms(DWORD op)
 }
 
 void
-SIDT_Ms(DWORD op)
+SIDT_Ms(UINT32 op)
 {
-	DWORD madr;
-	DWORD base;
-	WORD limit;
+	UINT32 madr;
+	UINT32 base;
+	UINT16 limit;
 
 	if (op < 0xc0) {
 		CPU_WORKCLOCK(11);
@@ -245,8 +247,8 @@ SIDT_Ms(DWORD op)
 void
 MOV_CdRd(void)
 {
-	DWORD op, src;
-	DWORD reg;
+	UINT32 op, src;
+	UINT32 reg;
 	int idx;
 
 	CPU_WORKCLOCK(11);
@@ -277,7 +279,7 @@ MOV_CdRd(void)
 			 */
 
 			/* 下巻 p.182 割り込み 13 - 一般保護例外 */
-			if ((src & (CPU_CR0_PE|CPU_CR0_PG)) == (DWORD)CPU_CR0_PG) {
+			if ((src & (CPU_CR0_PE|CPU_CR0_PG)) == (UINT32)CPU_CR0_PG) {
 				EXCEPTION(GP_EXCEPTION, 0);
 			}
 			if ((src & (CPU_CR0_NW|CPU_CR0_CD)) == CPU_CR0_NW) {
@@ -285,9 +287,10 @@ MOV_CdRd(void)
 			}
 
 			reg = CPU_CR0;
-			src &= 0xe005003f;
+			src &= CPU_CR0_ALL;
 #ifndef USE_FPU
-			src &= ~CPU_CR0_ET;	/* FPU not present */
+			src |= CPU_CR0_EM | CPU_CR0_NE;
+			src &= ~(CPU_CR0_MP | CPU_CR0_ET);
 #else
 			src |= CPU_CR0_ET;	/* FPU present */
 #endif
@@ -315,7 +318,7 @@ MOV_CdRd(void)
 				}
 			}
 
-			CPU_STAT_WP = (BYTE)((CPU_CR0 & CPU_CR0_WP) >> 12);
+			CPU_STAT_WP = (CPU_CR0 & CPU_CR0_WP) ? 0x10 : 0;
 			break;
 
 		case 2: /* CR2 */
@@ -381,15 +384,15 @@ MOV_CdRd(void)
 void
 MOV_RdCd(void)
 {
-	DWORD *out;
-	DWORD op;
+	UINT32 *out;
+	UINT32 op;
 	int idx;
 
 	CPU_WORKCLOCK(11);
 	GET_PCBYTE(op);
 	if (op >= 0xc0) {
 		if (CPU_STAT_PM && (CPU_STAT_VM86 || CPU_STAT_CPL != 0)) {
-			VERBOSE(("MOV_CdRd: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
+			VERBOSE(("MOV_RdCd: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
 			EXCEPTION(GP_EXCEPTION, 0);
 		}
 
@@ -427,10 +430,10 @@ MOV_RdCd(void)
 }
 
 void
-LMSW_Ew(DWORD op)
+LMSW_Ew(UINT32 op)
 {
-	DWORD src, madr;
-	DWORD cr0;
+	UINT32 src, madr;
+	UINT32 cr0;
 
 	if (!CPU_STAT_PM || CPU_STAT_CPL == 0) {
 		if (op >= 0xc0) {
@@ -455,17 +458,17 @@ LMSW_Ew(DWORD op)
 }
 
 void
-SMSW_Ew(DWORD op)
+SMSW_Ew(UINT32 op)
 {
-	DWORD madr;
+	UINT32 madr;
 
 	if (op >= 0xc0) {
 		CPU_WORKCLOCK(2);
-		*(reg16_b20[op]) = (WORD)CPU_CR0;
+		*(reg16_b20[op]) = (UINT16)CPU_CR0;
 	} else {
 		CPU_WORKCLOCK(3);
 		madr = calc_ea_dst(op);
-		cpu_vmemorywrite_w(CPU_INST_SEGREG_INDEX, madr, (WORD)CPU_CR0);
+		cpu_vmemorywrite_w(CPU_INST_SEGREG_INDEX, madr, (UINT16)CPU_CR0);
 	}
 }
 
@@ -473,7 +476,7 @@ void
 CLTS(void)
 {
 
-	CPU_WORKCLOCK(2);
+	CPU_WORKCLOCK(5);
 	if (CPU_STAT_PM && (CPU_STAT_VM86 || (CPU_STAT_CPL != 0))) {
 		VERBOSE(("CLTS: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
 		EXCEPTION(GP_EXCEPTION, 0);
@@ -484,7 +487,8 @@ CLTS(void)
 void
 ARPL_EwGw(void)
 {
-	DWORD op, src, dst, madr;
+	UINT32 op, madr;
+	UINT src, dst;
 
 	if (CPU_STAT_PM && !CPU_STAT_VM86) {
 		PREPART_EA_REG16(op, src);
@@ -495,7 +499,7 @@ ARPL_EwGw(void)
 				CPU_FLAGL |= Z_FLAG;
 				dst &= ~3;
 				dst |= (src & 3);
-				*(reg16_b20[op]) = (WORD)dst;
+				*(reg16_b20[op]) = (UINT16)dst;
 			} else {
 				CPU_FLAGL &= ~Z_FLAG;
 			}
@@ -507,7 +511,7 @@ ARPL_EwGw(void)
 				CPU_FLAGL |= Z_FLAG;
 				dst &= ~3;
 				dst |= (src & 3);
-				cpu_vmemorywrite_w(CPU_INST_SEGREG_INDEX, madr, (WORD)dst);
+				cpu_vmemorywrite_w(CPU_INST_SEGREG_INDEX, madr, (UINT16)dst);
 			} else {
 				CPU_FLAGL &= ~Z_FLAG;
 			}
@@ -525,11 +529,11 @@ void
 LAR_GwEw(void)
 {
 	selector_t sel;
-	WORD *out;
-	DWORD op;
-	DWORD h;
+	UINT16 *out;
+	UINT32 op;
+	UINT32 h;
 	int rv;
-	WORD selector;
+	UINT16 selector;
 
 	if (CPU_STAT_PM && !CPU_STAT_VM86) {
 		PREPART_REG16_EA(op, selector, out, 5, 11);
@@ -570,7 +574,7 @@ LAR_GwEw(void)
 		}
 
 		h = cpu_kmemoryread_d(sel.addr + 4);
-		*out = (WORD)(h & 0xff00);
+		*out = (UINT16)(h & 0xff00);
 		CPU_FLAGL |= Z_FLAG;
 		return;
 	}
@@ -582,16 +586,16 @@ void
 LAR_GdEw(void)
 {
 	selector_t sel;
-	DWORD *out;
-	DWORD op;
-	DWORD h;
+	UINT32 *out;
+	UINT32 op;
+	UINT32 h;
 	int rv;
-	DWORD selector;
+	UINT32 selector;
 
 	if (CPU_STAT_PM && !CPU_STAT_VM86) {
 		PREPART_REG32_EA(op, selector, out, 5, 11);
 
-		rv = parse_selector(&sel, (WORD)selector);
+		rv = parse_selector(&sel, (UINT16)selector);
 		if (rv < 0) {
 			CPU_FLAGL &= ~Z_FLAG;
 			return;
@@ -639,10 +643,10 @@ void
 LSL_GwEw(void)
 {
 	selector_t sel;
-	WORD *out;
-	DWORD op;
+	UINT16 *out;
+	UINT32 op;
 	int rv;
-	WORD selector;
+	UINT16 selector;
 
 	if (CPU_STAT_PM && !CPU_STAT_VM86) {
 		PREPART_REG16_EA(op, selector, out, 5, 11);
@@ -679,7 +683,7 @@ LSL_GwEw(void)
 			}
 		}
 
-		*out = (WORD)sel.desc.u.seg.limit;
+		*out = (UINT16)sel.desc.u.seg.limit;
 		CPU_FLAGL |= Z_FLAG;
 		return;
 	}
@@ -691,15 +695,15 @@ void
 LSL_GdEw(void)
 {
 	selector_t sel;
-	DWORD *out;
-	DWORD op;
+	UINT32 *out;
+	UINT32 op;
 	int rv;
-	DWORD selector;
+	UINT32 selector;
 
 	if (CPU_STAT_PM && !CPU_STAT_VM86) {
 		PREPART_REG32_EA(op, selector, out, 5, 11);
 
-		rv = parse_selector(&sel, (WORD)selector);
+		rv = parse_selector(&sel, (UINT16)selector);
 		if (rv < 0) {
 			CPU_FLAGL &= ~Z_FLAG;
 			return;
@@ -740,12 +744,12 @@ LSL_GdEw(void)
 }
 
 void
-VERR_Ew(DWORD op)
+VERR_Ew(UINT32 op)
 {
 	selector_t sel;
-	DWORD madr;
+	UINT32 madr;
 	int rv;
-	WORD selector;
+	UINT16 selector;
 
 	if (CPU_STAT_PM && !CPU_STAT_VM86) {
 		if (op >= 0xc0) {
@@ -791,12 +795,12 @@ VERR_Ew(DWORD op)
 }
 
 void
-VERW_Ew(DWORD op)
+VERW_Ew(UINT32 op)
 {
 	selector_t sel;
-	DWORD madr;
+	UINT32 madr;
 	int rv;
-	WORD selector;
+	UINT16 selector;
 
 	if (CPU_STAT_PM && !CPU_STAT_VM86) {
 		if (op >= 0xc0) {
@@ -840,15 +844,142 @@ VERW_Ew(DWORD op)
 void
 MOV_DdRd(void)
 {
+	UINT32 src;
+	UINT op;
+	int idx;
+#if defined(IA32_SUPPORT_DEBUG_REGISTER)
+	int i;
+#endif
+
+	CPU_WORKCLOCK(11);
+	GET_PCBYTE(op);
+	if (op >= 0xc0) {
+		if (CPU_STAT_PM && (CPU_STAT_VM86 || CPU_STAT_CPL != 0)) {
+			VERBOSE(("MOV_DdRd: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
+			EXCEPTION(GP_EXCEPTION, 0);
+		}
+
+		if (CPU_DR7 & CPU_DR7_GD) {
+			CPU_DR6 |= CPU_DR6_BD;
+			CPU_DR7 &= ~CPU_DR7_GD;
+			EXCEPTION(DB_EXCEPTION, 0);
+		}
 
-	ia32_panic("MOV_DdRd: not implemented yet!");
+		src = *(reg32_b20[op]);
+		idx = (op >> 3) & 7;
+
+		CPU_DR(idx) = src;
+		switch (idx) {
+		case 0:
+		case 1:
+		case 2:
+		case 3:
+			CPU_DR(idx) = src;
+			break;
+
+#if CPU_FAMILY >= 5
+		case 4:
+			if (CPU_CR4 & CPU_CR4_DE) {
+				EXCEPTION(UD_EXCEPTION, 0);
+			}
+#endif
+		case 6:
+			CPU_DR6 = src;
+			break;
+
+#if CPU_FAMILY >= 5
+		case 5:
+			if (CPU_CR4 & CPU_CR4_DE) {
+				EXCEPTION(UD_EXCEPTION, 0);
+			}
+#endif
+		case 7:
+			CPU_DR7 = src;
+			CPU_STAT_BP = 0;
+#if defined(IA32_SUPPORT_DEBUG_REGISTER)
+			for (i = 0; i < CPU_DEBUG_REG_INDEX_NUM; i++) {
+				if (CPU_DR7 & (CPU_DR7_L(i)|CPU_DR7_G(i))) {
+					CPU_STAT_BP |= (1 << i);
+				}
+			}
+#endif	/* IA32_SUPPORT_DEBUG_REGISTER */
+			break;
+
+		default:
+			ia32_panic("MOV_DdRd: DR reg index (%d)", idx);
+			/*NOTREACHED*/
+			break;
+		}
+
+		return;
+	}
+	EXCEPTION(UD_EXCEPTION, 0);
 }
 
 void
 MOV_RdDd(void)
 {
+	UINT32 *out;
+	UINT op;
+	int idx;
 
-	ia32_panic("MOV_DdRd: not implemented yet!");
+	CPU_WORKCLOCK(11);
+	GET_PCBYTE(op);
+	if (op >= 0xc0) {
+		if (CPU_STAT_PM && (CPU_STAT_VM86 || CPU_STAT_CPL != 0)) {
+			VERBOSE(("MOV_RdDd: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
+			EXCEPTION(GP_EXCEPTION, 0);
+		}
+
+		if (CPU_DR7 & CPU_DR7_GD) {
+			CPU_DR6 |= CPU_DR6_BD;
+			CPU_DR7 &= ~CPU_DR7_GD;
+			EXCEPTION(DB_EXCEPTION, 0);
+		}
+
+		out = reg32_b20[op];
+		idx = (op >> 3) & 7;
+
+		switch (idx) {
+		case 0:
+		case 1:
+		case 2:
+		case 3:
+			*out = CPU_DR(idx);
+			break;
+
+		case 4:
+#if CPU_FAMILY >= 5
+			if (CPU_CR4 & CPU_CR4_DE) {
+				EXCEPTION(UD_EXCEPTION, 0);
+			}
+#endif
+		case 6:
+#if CPU_FAMILY == 4
+			*out = (CPU_DR6 & 0x0000f00f) | 0xffff0ff0;
+#elif CPU_FAMILY >= 5
+			*out = (CPU_DR6 & 0x0000e00f) | 0xffff0ff0;
+#endif
+			break;
+
+#if CPU_FAMILY >= 5
+		case 5:
+			if (CPU_CR4 & CPU_CR4_DE) {
+				EXCEPTION(UD_EXCEPTION, 0);
+			}
+#endif
+		case 7:
+			*out = CPU_DR7;
+			break;
+
+		default:
+			ia32_panic("MOV_RdDd: DR reg index (%d)", idx);
+			/*NOTREACHED*/
+			break;
+		}
+		return;
+	}
+	EXCEPTION(UD_EXCEPTION, 0);
 }
 
 void
@@ -860,7 +991,8 @@ INVD(void)
 		VERBOSE(("INVD: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
 		EXCEPTION(GP_EXCEPTION, 0);
 	}
-	/* nothing to do */
+
+	tlb_flush(TRUE);
 }
 
 void
@@ -872,13 +1004,17 @@ WBINVD(void)
 		VERBOSE(("WBINVD: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
 		EXCEPTION(GP_EXCEPTION, 0);
 	}
-	/* nothing to do */
+
+	tlb_flush(TRUE);
 }
 
 void
-INVLPG(DWORD op)
+INVLPG(UINT32 op)
 {
-	DWORD madr;
+	descriptor_t *sd;
+	UINT32 madr;
+	int idx;
+	int exc;
 
 	if (CPU_STAT_PM && (CPU_STAT_VM86 || CPU_STAT_CPL != 0)) {
 		VERBOSE(("INVLPG: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
@@ -888,10 +1024,40 @@ INVLPG(DWORD op)
 	if (op < 0xc0) {
 		CPU_WORKCLOCK(11);
 		madr = calc_ea_dst(op);
-		tlb_flush_page(madr);
+
+		idx = CPU_INST_SEGREG_INDEX;
+		sd = &CPU_STAT_SREG(idx);
+		if (!sd->valid) {
+			exc = GP_EXCEPTION;
+			goto err;
+		}
+		switch (sd->type) {
+		case 4: case 5: case 6: case 7:
+			if (madr <= sd->u.seg.limit) {
+				if (idx == CPU_SS_INDEX)
+					exc = SS_EXCEPTION;
+				else
+					exc = GP_EXCEPTION;
+				goto err;
+			}
+			break;
+
+		default:
+			if (madr > sd->u.seg.limit) {
+				if (idx == CPU_SS_INDEX)
+					exc = SS_EXCEPTION;
+				else
+					exc = GP_EXCEPTION;
+				goto err;
+			}
+			break;
+		}
+		tlb_flush_page(sd->u.seg.segbase + madr);
 		return;
 	}
-	EXCEPTION(UD_EXCEPTION, 0);
+	exc = UD_EXCEPTION;
+err:
+	EXCEPTION(exc, 0);
 }
 
 void
@@ -912,6 +1078,9 @@ HLT(void)
 
 	CPU_HALT();
 	CPU_EIP--;
+#if defined(IA32_SUPPORT_PREFETCH_QUEUE)
+	CPU_PREFETCHQ_REMAIN++;
+#endif
 	CPU_STAT_HLT = 1;
 }