--- np2/i386c/ia32/instructions/system_inst.c	2004/03/12 13:34:08	1.24
+++ np2/i386c/ia32/instructions/system_inst.c	2008/01/25 18:02:18	1.32
@@ -1,4 +1,4 @@
-/*	$Id: system_inst.c,v 1.24 2004/03/12 13:34:08 monaka Exp $	*/
+/*	$Id: system_inst.c,v 1.32 2008/01/25 18:02:18 monaka Exp $	*/
 
 /*
  * Copyright (c) 2003 NONAKA Kimihiro
@@ -12,8 +12,6 @@
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
@@ -142,7 +140,8 @@ SLDT_Ew(UINT32 op)
 void
 LTR_Ew(UINT32 op)
 {
-	UINT32 src, madr;
+	UINT32 madr;
+	UINT16 src;
 
 	if (CPU_STAT_PM && !CPU_STAT_VM86) {
 		if (CPU_STAT_CPL == 0) {
@@ -154,7 +153,7 @@ LTR_Ew(UINT32 op)
 				madr = calc_ea_dst(op);
 				src = cpu_vmemoryread_w(CPU_INST_SEGREG_INDEX, madr);
 			}
-			load_tr((UINT16)src);
+			load_tr(src);
 			return;
 		}
 		VERBOSE(("LTR: CPL(%d) != 0", CPU_STAT_CPL));
@@ -286,17 +285,18 @@ MOV_CdRd(void)
 			}
 
 			reg = CPU_CR0;
-			src &= 0xe005003f;
-#ifndef USE_FPU
-			src &= ~CPU_CR0_ET;	/* FPU not present */
-#else
+			src &= CPU_CR0_ALL;
+#if defined(USE_FPU)
 			src |= CPU_CR0_ET;	/* FPU present */
+#else
+			src |= CPU_CR0_EM | CPU_CR0_NE;
+			src &= ~(CPU_CR0_MP | CPU_CR0_ET);
 #endif
 			CPU_CR0 = src;
 			VERBOSE(("MOV_CdRd: %04x:%08x: cr0: 0x%08x <- 0x%08x(%s)", CPU_CS, CPU_PREV_EIP, reg, CPU_CR0, reg32_str[op & 7]));
 
 			if ((reg ^ CPU_CR0) & (CPU_CR0_PE|CPU_CR0_PG)) {
-				tlb_flush(FALSE);
+				tlb_flush(TRUE);
 			}
 			if ((reg ^ CPU_CR0) & CPU_CR0_PE) {
 				if (CPU_CR0 & CPU_CR0_PE) {
@@ -336,7 +336,6 @@ MOV_CdRd(void)
 			VERBOSE(("MOV_CdRd: %04x:%08x: cr3: 0x%08x <- 0x%08x(%s)", CPU_CS, CPU_PREV_EIP, reg, CPU_CR3, reg32_str[op & 7]));
 			break;
 
-#if CPU_FAMILY >= 5
 		case 4: /* CR4 */
 			/*
 			 * 10 = OSXMMEXCPT (support non masking exception by OS)
@@ -351,7 +350,11 @@ MOV_CdRd(void)
 			 * 1 = PVI (protected mode virtual interrupt)
 			 * 0 = VME (VM8086 mode extention)
 			 */
-			reg = 0;	/* allow */
+			reg = 0		/* allow bit */
+#if (CPU_FEATURES & CPU_FEATURE_PGE) == CPU_FEATURE_PGE
+			    | CPU_CR4_PGE
+#endif
+			;
 			if (src & ~reg) {
 				if (src & 0xfffffc00) {
 					EXCEPTION(GP_EXCEPTION, 0);
@@ -364,10 +367,9 @@ MOV_CdRd(void)
 			VERBOSE(("MOV_CdRd: %04x:%08x: cr4: 0x%08x <- 0x%08x(%s)", CPU_CS, CPU_PREV_EIP, reg, CPU_CR4, reg32_str[op & 7]));
 
 			if ((reg ^ CPU_CR4) & (CPU_CR4_PSE|CPU_CR4_PGE|CPU_CR4_PAE)) {
-				tlb_flush(FALSE);
+				tlb_flush(TRUE);
 			}
 			break;
-#endif	/* CPU_FAMILY >= 5 */
 
 		default:
 			ia32_panic("MOV_CdRd: CR reg index (%d)", idx);
@@ -410,11 +412,9 @@ MOV_RdCd(void)
 			*out = CPU_CR3;
 			break;
 
-#if CPU_FAMILY >= 5
 		case 4:
 			*out = CPU_CR4;
 			break;
-#endif	/* CPU_FAMILY >= 5 */
 
 		default:
 			ia32_panic("MOV_RdCd: CR reg index (%d)", idx);
@@ -485,8 +485,8 @@ CLTS(void)
 void
 ARPL_EwGw(void)
 {
-	UINT32 op, src, madr;
-	UINT16 dst;
+	UINT32 op, madr;
+	UINT src, dst;
 
 	if (CPU_STAT_PM && !CPU_STAT_VM86) {
 		PREPART_EA_REG16(op, src);
@@ -497,7 +497,7 @@ ARPL_EwGw(void)
 				CPU_FLAGL |= Z_FLAG;
 				dst &= ~3;
 				dst |= (src & 3);
-				*(reg16_b20[op]) = dst;
+				*(reg16_b20[op]) = (UINT16)dst;
 			} else {
 				CPU_FLAGL &= ~Z_FLAG;
 			}
@@ -509,7 +509,7 @@ ARPL_EwGw(void)
 				CPU_FLAGL |= Z_FLAG;
 				dst &= ~3;
 				dst |= (src & 3);
-				cpu_vmemorywrite_w(CPU_INST_SEGREG_INDEX, madr, dst);
+				cpu_vmemorywrite_w(CPU_INST_SEGREG_INDEX, madr, (UINT16)dst);
 			} else {
 				CPU_FLAGL &= ~Z_FLAG;
 			}
@@ -845,7 +845,9 @@ MOV_DdRd(void)
 	UINT32 src;
 	UINT op;
 	int idx;
+#if defined(IA32_SUPPORT_DEBUG_REGISTER)
 	int i;
+#endif
 
 	CPU_WORKCLOCK(11);
 	GET_PCBYTE(op);
@@ -987,8 +989,6 @@ INVD(void)
 		VERBOSE(("INVD: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
 		EXCEPTION(GP_EXCEPTION, 0);
 	}
-
-	tlb_flush(TRUE);
 }
 
 void
@@ -1000,8 +1000,6 @@ WBINVD(void)
 		VERBOSE(("WBINVD: VM86(%s) or CPL(%d) != 0", CPU_STAT_VM86 ? "true" : "false", CPU_STAT_CPL));
 		EXCEPTION(GP_EXCEPTION, 0);
 	}
-
-	tlb_flush(TRUE);
 }
 
 void
@@ -1074,9 +1072,6 @@ HLT(void)
 
 	CPU_HALT();
 	CPU_EIP--;
-#if defined(IA32_SUPPORT_PREFETCH_QUEUE)
-	CPU_PREFETCHQ_REMAIN++;
-#endif
 	CPU_STAT_HLT = 1;
 }
 
@@ -1117,7 +1112,7 @@ WRMSR(void)
 
 	idx = CPU_ECX;
 	switch (idx) {
-		/* MTRR への書き込み時 tlb_flush(FALSE); */
+		/* MTRR への書き込み時 tlb_flush(TRUE); */
 
 	default:
 		EXCEPTION(GP_EXCEPTION, 0);