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| version 1.14, 2004/03/05 14:17:35 | version 1.21, 2004/05/23 15:01:45 |
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| Line 31 | Line 31 |
| #include "cpu.h" | #include "cpu.h" |
| #include "ia32.mcr" | #include "ia32.mcr" |
| #include "pccore.h" | |
| #include "iocore.h" | |
| #include "dmap.h" | #include "dmap.h" |
| #include "bios.h" | #include "bios.h" |
| #if defined(IA32_REBOOT_ON_PANIC) | #if defined(IA32_REBOOT_ON_PANIC) |
| Line 58 ia32_initreg(void) | Line 60 ia32_initreg(void) |
| #if CPU_FAMILY == 4 | #if CPU_FAMILY == 4 |
| CPU_STATSAVE.cpu_regs.dr[6] = 0xffff1ff0; | CPU_STATSAVE.cpu_regs.dr[6] = 0xffff1ff0; |
| #elif (CPU_FAMILY == 5) || (CPU_FAMILY == 6) | #elif CPU_FAMILY >= 5 |
| CPU_STATSAVE.cpu_regs.dr[6] = 0xffff0ff0; | CPU_STATSAVE.cpu_regs.dr[6] = 0xffff0ff0; |
| CPU_STATSAVE.cpu_regs.dr[7] = 0x00000400; | CPU_STATSAVE.cpu_regs.dr[7] = 0x00000400; |
| #endif | #endif |
| Line 93 ia32shut(void) | Line 95 ia32shut(void) |
| } | } |
| void | void |
| ia32(void) | ia32a20enable(BOOL enable) |
| { | { |
| int rv; | #if (CPU_FAMILY == 3) |
| CPU_ADRSMASK = (enable)?0x00ffffff:0x00ffffff; | |
| rv = sigsetjmp(exec_1step_jmpbuf, 1); | #else |
| switch (rv) { | CPU_ADRSMASK = (enable)?0xffffffff:0x00ffffff; |
| case 0: | #endif |
| break; | |
| case 1: | |
| VERBOSE(("ia32: return from exception")); | |
| break; | |
| case 2: | |
| VERBOSE(("ia32: return from panic")); | |
| return; | |
| default: | |
| VERBOSE(("ia32: return from unknown cause")); | |
| break; | |
| } | |
| do { | |
| exec_1step(); | |
| } while (CPU_REMCLOCK > 0); | |
| } | } |
| void | void |
| ia32withtrap(void) | ia32(void) |
| { | { |
| int rv; | int rv; |
| Line 131 ia32withtrap(void) | Line 115 ia32withtrap(void) |
| break; | break; |
| case 1: | case 1: |
| VERBOSE(("ia32withtrap: return from exception")); | VERBOSE(("ia32: return from exception")); |
| break; | break; |
| case 2: | case 2: |
| VERBOSE(("ia32withtrap: return from panic")); | VERBOSE(("ia32: return from panic")); |
| return; | return; |
| default: | default: |
| VERBOSE(("ia32withtrap: return from unknown cause")); | VERBOSE(("ia32: return from unknown cause")); |
| break; | break; |
| } | } |
| #if defined(IA32_SUPPORT_DEBUG_REGISTER) | |
| do { | do { |
| exec_1step(); | exec_1step(); |
| if (CPU_TRAP) { | if (dmac.working) { |
| ia32_interrupt(1); | dmap(); |
| } | } |
| } while (CPU_REMCLOCK > 0); | } while (CPU_REMCLOCK > 0); |
| } | #else |
| if (CPU_TRAP) { | |
| void | do { |
| ia32withdma(void) | exec_1step(); |
| { | if (CPU_TRAP) { |
| int rv; | CPU_DR6 |= CPU_DR6_BS; |
| INTERRUPT(1, TRUE, FALSE, 0); | |
| rv = sigsetjmp(exec_1step_jmpbuf, 1); | } |
| switch (rv) { | dmap(); |
| case 0: | } while (CPU_REMCLOCK > 0); |
| break; | } else if (dmac.working) { |
| do { | |
| case 1: | exec_1step(); |
| VERBOSE(("ia32withdma: return from exception")); | dmap(); |
| break; | } while (CPU_REMCLOCK > 0); |
| } else { | |
| case 2: | do { |
| VERBOSE(("ia32withdma: return from panic")); | exec_1step(); |
| return; | } while (CPU_REMCLOCK > 0); |
| default: | |
| VERBOSE(("ia32withdma: return from unknown cause")); | |
| break; | |
| } | } |
| #endif | |
| do { | |
| exec_1step(); | |
| dmap_i286(); | |
| } while (CPU_REMCLOCK > 0); | |
| } | } |
| void | void |
| Line 205 ia32_step(void) | Line 182 ia32_step(void) |
| do { | do { |
| exec_1step(); | exec_1step(); |
| #if !defined(IA32_SUPPORT_DEBUG_REGISTER) | |
| if (CPU_TRAP) { | if (CPU_TRAP) { |
| ia32_interrupt(1); | CPU_DR6 |= CPU_DR6_BS; |
| INTERRUPT(1, TRUE, FALSE, 0); | |
| } | |
| #endif | |
| if (dmac.working) { | |
| dmap(); | |
| } | } |
| dmap_i286(); | |
| } while (CPU_REMCLOCK > 0); | } while (CPU_REMCLOCK > 0); |
| } | } |
| void CPUCALL | void CPUCALL |
| ia32_interrupt(int vect) | ia32_interrupt(int vect, int soft) |
| { | { |
| INTERRUPT(vect, 0, 0, 0); | // TRACEOUT(("int (%x, %x) PE=%d VM=%d", vect, soft, CPU_STAT_PM, CPU_STAT_VM86)); |
| if (!soft) { | |
| INTERRUPT(vect, FALSE, FALSE, 0); | |
| } | |
| else { | |
| if (CPU_STAT_VM86 && (CPU_STAT_IOPL < CPU_IOPL3) && (soft == -1)) { | |
| TRACEOUT(("BIOS interrupt: VM86 && IOPL < 3 && INTn")); | |
| } | |
| INTERRUPT(vect, TRUE, FALSE, 0); | |
| } | |
| } | } |
| Line 240 ia32_panic(const char *str, ...) | Line 231 ia32_panic(const char *str, ...) |
| #if defined(IA32_REBOOT_ON_PANIC) | #if defined(IA32_REBOOT_ON_PANIC) |
| VERBOSE(("ia32_panic: reboot")); | VERBOSE(("ia32_panic: reboot")); |
| pccore_cfgupdate(); | |
| pccore_reset(); | pccore_reset(); |
| siglongjmp(exec_1step_jmpbuf, 2); | siglongjmp(exec_1step_jmpbuf, 2); |
| #else | #else |
| Line 285 ia32_bioscall(void) | Line 275 ia32_bioscall(void) |
| UINT32 adrs; | UINT32 adrs; |
| if (!CPU_STAT_PM || CPU_STAT_VM86) { | if (!CPU_STAT_PM || CPU_STAT_VM86) { |
| #if 1 | |
| adrs = (CPU_EIP - 1) + ((CPU_REGS_SREG(CPU_CS_INDEX)) << 4); | |
| #else | |
| adrs = (CPU_EIP - 1) + CPU_STAT_CS_BASE; | adrs = (CPU_EIP - 1) + CPU_STAT_CS_BASE; |
| #endif | |
| if ((adrs >= 0xf8000) && (adrs < 0x100000)) { | if ((adrs >= 0xf8000) && (adrs < 0x100000)) { |
| biosfunc(adrs); | if (biosfunc(adrs)) { |
| CPU_PREFETCH_CLEAR(); | |
| } | |
| if (!CPU_STAT_PM || CPU_STAT_VM86) { | if (!CPU_STAT_PM || CPU_STAT_VM86) { |
| CPU_SET_SEGREG(CPU_ES_INDEX, CPU_ES); | CPU_SET_SEGREG(CPU_ES_INDEX, CPU_ES); |
| CPU_SET_SEGREG(CPU_CS_INDEX, CPU_CS); | CPU_SET_SEGREG(CPU_CS_INDEX, CPU_CS); |