np2/i386c/ia32/interface.c - diff

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Diff for /np2/i386c/ia32/interface.c between versions 1.17 and 1.31

version 1.17, 2004/03/08 12:56:22	version 1.31, 2012/01/08 11:36:06
Line 1	Line 1
/* $Id$ */

/*	/*
* Copyright (c) 2002-2003 NONAKA Kimihiro	* Copyright (c) 2002-2003 NONAKA Kimihiro
* All rights reserved.	* All rights reserved.
Line 12	Line 10
* 2. Redistributions in binary form must reproduce the above copyright	* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the	* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.	* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*	*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
Line 30	Line 26
#include "compiler.h"	#include "compiler.h"
#include "cpu.h"	#include "cpu.h"
#include "ia32.mcr"	#include "ia32.mcr"
	#if defined(USE_FPU)
	#include "instructions/fpu/fp.h"
	#endif

#include "pccore.h"	#include "pccore.h"
#include "iocore.h"	#include "iocore.h"
#include "dmap.h"	#include "dmax86.h"
#include "bios.h"	#include "bios.h"
#if defined(IA32_REBOOT_ON_PANIC)
#include "pccore.h"
#endif


void	void
Line 50 ia32_initreg(void)	Line 46 ia32_initreg(void)
CPU_EDX = (CPU_FAMILY << 8) \| (CPU_MODEL << 4) \| CPU_STEPPING;	CPU_EDX = (CPU_FAMILY << 8) \| (CPU_MODEL << 4) \| CPU_STEPPING;
CPU_EFLAG = 2;	CPU_EFLAG = 2;
CPU_CR0 = CPU_CR0_CD \| CPU_CR0_NW \| CPU_CR0_ET;	CPU_CR0 = CPU_CR0_CD \| CPU_CR0_NW \| CPU_CR0_ET;
#ifndef USE_FPU	#if defined(USE_FPU)
	CPU_CR0 \|= CPU_CR0_ET;
	#else
CPU_CR0 \|= CPU_CR0_EM \| CPU_CR0_NE;	CPU_CR0 \|= CPU_CR0_EM \| CPU_CR0_NE;
CPU_CR0 &= ~CPU_CR0_MP;	CPU_CR0 &= ~(CPU_CR0_MP \| CPU_CR0_ET);
#endif	#endif
CPU_MXCSR = 0x1f80;	CPU_MXCSR = 0x1f80;

	CPU_GDTR_BASE = 0x0;
CPU_GDTR_LIMIT = 0xffff;	CPU_GDTR_LIMIT = 0xffff;
	CPU_IDTR_BASE = 0x0;
CPU_IDTR_LIMIT = 0xffff;	CPU_IDTR_LIMIT = 0xffff;
	CPU_LDTR_BASE = 0x0;
	CPU_LDTR_LIMIT = 0xffff;
	CPU_TR_BASE = 0x0;
	CPU_TR_LIMIT = 0xffff;

#if CPU_FAMILY == 4
CPU_STATSAVE.cpu_regs.dr[6] = 0xffff1ff0;	CPU_STATSAVE.cpu_regs.dr[6] = 0xffff1ff0;
#elif CPU_FAMILY >= 5
CPU_STATSAVE.cpu_regs.dr[6] = 0xffff0ff0;
CPU_STATSAVE.cpu_regs.dr[7] = 0x00000400;
#endif

for (i = 0; i < CPU_SEGREG_NUM; ++i) {	for (i = 0; i < CPU_SEGREG_NUM; ++i) {
CPU_STAT_SREG_INIT(i);	segdesc_init(i, 0, &CPU_STAT_SREG(i));
}	}
CPU_LDTR_LIMIT = 0xffff;	LOAD_SEGREG(CPU_CS_INDEX, 0xf000);
CPU_TR_LIMIT = 0xffff;	CPU_STAT_CS_BASE = 0xffff0000;

CPU_SET_SEGREG(CPU_CS_INDEX, 0xf000);
CPU_EIP = 0xfff0;	CPU_EIP = 0xfff0;
CPU_ADRSMASK = 0x000fffff;	CPU_ADRSMASK = 0x000fffff;

tlb_init();	tlb_init();
	#if defined(USE_FPU)
	fpu_init();
	#endif
}	}

void	void
Line 95 ia32shut(void)	Line 96 ia32shut(void)
}	}

void	void
	ia32a20enable(BOOL enable)
	{

	CPU_ADRSMASK = (enable)?0xffffffff:0x00ffffff;
	}

	void
ia32(void)	ia32(void)
{	{
int rv;	int rv;
Line 117 ia32(void)	Line 125 ia32(void)
break;	break;
}	}

#if defined(IA32_SUPPORT_DEBUG_REGISTER)
do {
exec_1step();
if (dmac.working) {
dmap();
}
} while (CPU_REMCLOCK > 0);
#else
if (CPU_TRAP) {	if (CPU_TRAP) {
do {	do {
exec_1step();	exec_1step();
if (CPU_TRAP) {	if (CPU_TRAP) {
CPU_DR6 \|= CPU_DR6_BS;	CPU_DR6 \|= CPU_DR6_BS;
INTERRUPT(1, TRUE, FALSE, 0);	INTERRUPT(1, INTR_TYPE_EXCEPTION);
}	}
dmap();	dmax86();
} while (CPU_REMCLOCK > 0);	} while (CPU_REMCLOCK > 0);
} else if (dmac.working) {	} else if (dmac.working) {
do {	do {
exec_1step();	exec_1step();
dmap();	dmax86();
} while (CPU_REMCLOCK > 0);	} while (CPU_REMCLOCK > 0);
} else {	} else {
do {	do {
exec_1step();	exec_1step();
} while (CPU_REMCLOCK > 0);	} while (CPU_REMCLOCK > 0);
}	}
#endif
}	}

void	void
Line 172 ia32_step(void)	Line 171 ia32_step(void)

do {	do {
exec_1step();	exec_1step();
#if !defined(IA32_SUPPORT_DEBUG_REGISTER)
if (CPU_TRAP) {	if (CPU_TRAP) {
CPU_DR6 \|= CPU_DR6_BS;	CPU_DR6 \|= CPU_DR6_BS;
INTERRUPT(1, TRUE, FALSE, 0);	INTERRUPT(1, INTR_TYPE_EXCEPTION);
}	}
#endif
if (dmac.working) {	if (dmac.working) {
dmap();	dmax86();
}	}
} while (CPU_REMCLOCK > 0);	} while (CPU_REMCLOCK > 0);
}	}

void CPUCALL	void CPUCALL
ia32_interrupt(int vect)	ia32_interrupt(int vect, int soft)
{	{

INTERRUPT(vect, FALSE, FALSE, 0);	// TRACEOUT(("int (%x, %x) PE=%d VM=%d", vect, soft, CPU_STAT_PM, CPU_STAT_VM86));
	if (!soft) {
	INTERRUPT(vect, INTR_TYPE_EXTINTR);
	} else {
	if (CPU_STAT_PM && CPU_STAT_VM86 && CPU_STAT_IOPL < CPU_IOPL3) {
	VERBOSE(("ia32_interrupt: VM86 && IOPL < 3 && INTn"));
	EXCEPTION(GP_EXCEPTION, 0);
	}
	INTERRUPT(vect, INTR_TYPE_SOFTINTR);
	}
}	}


Line 256 ia32_bioscall(void)	Line 262 ia32_bioscall(void)
UINT32 adrs;	UINT32 adrs;

if (!CPU_STAT_PM \|\| CPU_STAT_VM86) {	if (!CPU_STAT_PM \|\| CPU_STAT_VM86) {
adrs = (CPU_EIP - 1) + CPU_STAT_CS_BASE;	#if 1
	adrs = CPU_PREV_EIP + (CPU_CS << 4);
	#else
	adrs = CPU_PREV_EIP + CPU_STAT_CS_BASE;
	#endif
if ((adrs >= 0xf8000) && (adrs < 0x100000)) {	if ((adrs >= 0xf8000) && (adrs < 0x100000)) {
biosfunc(adrs);	if (biosfunc(adrs)) {
if (!CPU_STAT_PM \|\| CPU_STAT_VM86) {	/* Nothing to do */
CPU_SET_SEGREG(CPU_ES_INDEX, CPU_ES);
CPU_SET_SEGREG(CPU_CS_INDEX, CPU_CS);
CPU_SET_SEGREG(CPU_SS_INDEX, CPU_SS);
CPU_SET_SEGREG(CPU_DS_INDEX, CPU_DS);
}	}
	LOAD_SEGREG(CPU_ES_INDEX, CPU_ES);
	LOAD_SEGREG(CPU_CS_INDEX, CPU_CS);
	LOAD_SEGREG(CPU_SS_INDEX, CPU_SS);
	LOAD_SEGREG(CPU_DS_INDEX, CPU_DS);
}	}
}	}
}	}

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Removed from v.1.17
changed lines
	Added in v.1.31