np2/i386c/ia32/interface.c - diff

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Diff for /np2/i386c/ia32/interface.c between versions 1.8 and 1.18

version 1.8, 2004/01/24 18:20:06	version 1.18, 2004/03/09 18:52:12
Line 31	Line 31
#include "cpu.h"	#include "cpu.h"
#include "ia32.mcr"	#include "ia32.mcr"

	#include "pccore.h"
	#include "iocore.h"
#include "dmap.h"	#include "dmap.h"
#include "bios.h"	#include "bios.h"
	#if defined(IA32_REBOOT_ON_PANIC)
	#include "pccore.h"
	#endif


static void ia32_initreg(void) {	void
	ia32_initreg(void)
	{
int i;	int i;

CPU_STATSAVE.cpu_inst_default.seg_base = (DWORD)-1;	CPU_STATSAVE.cpu_inst_default.seg_base = (UINT32)-1;

CPU_EDX = (CPU_FAMILY << 8) \| (CPU_MODEL << 4) \| CPU_STEPPING;	CPU_EDX = (CPU_FAMILY << 8) \| (CPU_MODEL << 4) \| CPU_STEPPING;
CPU_EFLAG = 2;	CPU_EFLAG = 2;
Line 54 static void ia32_initreg(void) {	Line 60 static void ia32_initreg(void) {

#if CPU_FAMILY == 4	#if CPU_FAMILY == 4
CPU_STATSAVE.cpu_regs.dr[6] = 0xffff1ff0;	CPU_STATSAVE.cpu_regs.dr[6] = 0xffff1ff0;
#elif (CPU_FAMILY == 5) \|\| (CPU_FAMILY == 6)	#elif CPU_FAMILY >= 5
CPU_STATSAVE.cpu_regs.dr[6] = 0xffff0ff0;	CPU_STATSAVE.cpu_regs.dr[6] = 0xffff0ff0;
CPU_STATSAVE.cpu_regs.dr[7] = 0x00000400;	CPU_STATSAVE.cpu_regs.dr[7] = 0x00000400;
#endif	#endif
Line 68 static void ia32_initreg(void) {	Line 74 static void ia32_initreg(void) {
CPU_SET_SEGREG(CPU_CS_INDEX, 0xf000);	CPU_SET_SEGREG(CPU_CS_INDEX, 0xf000);
CPU_EIP = 0xfff0;	CPU_EIP = 0xfff0;
CPU_ADRSMASK = 0x000fffff;	CPU_ADRSMASK = 0x000fffff;

	tlb_init();
}	}

void	void
ia32reset(void)	ia32reset(void)
{	{
ZeroMemory(&i386core.s, sizeof(i386core.s));
	memset(&i386core.s, 0, sizeof(i386core.s));
ia32_initreg();	ia32_initreg();
}	}

void	void
ia32shut(void)	ia32shut(void)
{	{
ZeroMemory(&i386core.s, offsetof(I386STAT, cpu_type));
	memset(&i386core.s, 0, offsetof(I386STAT, cpu_type));
ia32_initreg();	ia32_initreg();
}	}

Line 98 ia32(void)	Line 108 ia32(void)
VERBOSE(("ia32: return from exception"));	VERBOSE(("ia32: return from exception"));
break;	break;

default:	case 2:
VERBOSE(("ia32: return from unknown cause"));	VERBOSE(("ia32: return from panic"));
break;	return;
}

do {
exec_1step();
} while (CPU_REMCLOCK > 0);
}

void
ia32withtrap(void)
{
int rv;

rv = sigsetjmp(exec_1step_jmpbuf, 1);
switch (rv) {
case 0:
break;

case 1:
VERBOSE(("ia32withtrap: return from exception"));
break;

default:	default:
VERBOSE(("ia32withtrap: return from unknown cause"));	VERBOSE(("ia32: return from unknown cause"));
break;	break;
}	}

	#if defined(IA32_SUPPORT_DEBUG_REGISTER)
do {	do {
exec_1step();	exec_1step();
if (CPU_TRAP) {	if (dmac.working) {
ia32_interrupt(1);	dmap();
}	}
} while (CPU_REMCLOCK > 0);	} while (CPU_REMCLOCK > 0);
}	#else
	if (CPU_TRAP) {
void	do {
ia32withdma(void)	exec_1step();
{	if (CPU_TRAP) {
int rv;	CPU_DR6 \|= CPU_DR6_BS;
	INTERRUPT(1, TRUE, FALSE, 0);
rv = sigsetjmp(exec_1step_jmpbuf, 1);	}
switch (rv) {	dmap();
case 0:	} while (CPU_REMCLOCK > 0);
break;	} else if (dmac.working) {
	do {
case 1:	exec_1step();
VERBOSE(("ia32withdma: return from exception"));	dmap();
break;	} while (CPU_REMCLOCK > 0);
	} else {
default:	do {
VERBOSE(("ia32withdma: return from unknown cause"));	exec_1step();
break;	} while (CPU_REMCLOCK > 0);
}	}
	#endif
do {
exec_1step();
dmap_i286();
} while (CPU_REMCLOCK > 0);
}	}

void	void
Line 174 ia32_step(void)	Line 161 ia32_step(void)
VERBOSE(("ia32_step: return from exception"));	VERBOSE(("ia32_step: return from exception"));
break;	break;

	case 2:
	VERBOSE(("ia32_step: return from panic"));
	return;

default:	default:
VERBOSE(("ia32_step: return from unknown cause"));	VERBOSE(("ia32_step: return from unknown cause"));
break;	break;
Line 181 ia32_step(void)	Line 172 ia32_step(void)

do {	do {
exec_1step();	exec_1step();
	#if !defined(IA32_SUPPORT_DEBUG_REGISTER)
if (CPU_TRAP) {	if (CPU_TRAP) {
ia32_interrupt(1);	CPU_DR6 \|= CPU_DR6_BS;
	INTERRUPT(1, TRUE, FALSE, 0);
	}
	#endif
	if (dmac.working) {
	dmap();
}	}
dmap_i286();
} while (CPU_REMCLOCK > 0);	} while (CPU_REMCLOCK > 0);
}	}

void CPUCALL	void CPUCALL
ia32_interrupt(BYTE vect)	ia32_interrupt(int vect)
{	{

INTERRUPT(vect, 0, 0, 0);	INTERRUPT(vect, FALSE, FALSE, 0);
}	}


Line 214 ia32_panic(const char *str, ...)	Line 210 ia32_panic(const char *str, ...)

msgbox("ia32_panic", buf);	msgbox("ia32_panic", buf);

	#if defined(IA32_REBOOT_ON_PANIC)
	VERBOSE(("ia32_panic: reboot"));
	pccore_reset();
	siglongjmp(exec_1step_jmpbuf, 2);
	#else
__ASSERT(0);	__ASSERT(0);
exit(1);	exit(1);
	#endif
}	}

void	void
Line 251 ia32_printf(const char *str, ...)	Line 253 ia32_printf(const char *str, ...)
void	void
ia32_bioscall(void)	ia32_bioscall(void)
{	{
DWORD adrs;	UINT32 adrs;

if (!CPU_STAT_PM && !CPU_INST_OP32 && !CPU_INST_AS32) {	if (!CPU_STAT_PM \|\| CPU_STAT_VM86) {
adrs = ((CPU_IP-1) & 0xffff) + CPU_STAT_SREGBASE(CPU_CS_INDEX);	#if 1
	adrs = (CPU_EIP - 1) + ((CPU_REGS_SREG(CPU_CS_INDEX)) << 4);
	#else
	adrs = (CPU_EIP - 1) + CPU_STAT_CS_BASE;
	#endif
if ((adrs >= 0xf8000) && (adrs < 0x100000)) {	if ((adrs >= 0xf8000) && (adrs < 0x100000)) {
biosfunc(adrs);	biosfunc(adrs);
CPU_SET_SEGREG(CPU_ES_INDEX, CPU_ES);	if (!CPU_STAT_PM \|\| CPU_STAT_VM86) {
CPU_SET_SEGREG(CPU_CS_INDEX, CPU_CS);	CPU_SET_SEGREG(CPU_ES_INDEX, CPU_ES);
CPU_SET_SEGREG(CPU_SS_INDEX, CPU_SS);	CPU_SET_SEGREG(CPU_CS_INDEX, CPU_CS);
CPU_SET_SEGREG(CPU_DS_INDEX, CPU_DS);	CPU_SET_SEGREG(CPU_SS_INDEX, CPU_SS);
	CPU_SET_SEGREG(CPU_DS_INDEX, CPU_DS);
	}
}	}
}	}
}	}

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Removed from v.1.8
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	Added in v.1.18