| version 1.10, 2004/02/04 13:24:35 | version 1.19, 2004/03/10 23:01:08 | 
| Line 31 | Line 31 | 
 | #include "cpu.h" | #include "cpu.h" | 
 | #include "ia32.mcr" | #include "ia32.mcr" | 
 |  |  | 
 |  | #include "pccore.h" | 
 |  | #include "iocore.h" | 
 | #include "dmap.h" | #include "dmap.h" | 
 | #include "bios.h" | #include "bios.h" | 
 | #if defined(IA32_REBOOT_ON_PANIC) | #if defined(IA32_REBOOT_ON_PANIC) | 
| Line 38 | Line 40 | 
 | #endif | #endif | 
 |  |  | 
 |  |  | 
| static void ia32_initreg(void) { | void | 
|  | ia32_initreg(void) | 
|  | { | 
 | int i; | int i; | 
 |  |  | 
| CPU_STATSAVE.cpu_inst_default.seg_base = (DWORD)-1; | CPU_STATSAVE.cpu_inst_default.seg_base = (UINT32)-1; | 
 |  |  | 
 | CPU_EDX = (CPU_FAMILY << 8) | (CPU_MODEL << 4) | CPU_STEPPING; | CPU_EDX = (CPU_FAMILY << 8) | (CPU_MODEL << 4) | CPU_STEPPING; | 
 | CPU_EFLAG = 2; | CPU_EFLAG = 2; | 
| Line 57  static void ia32_initreg(void) { | Line 60  static void ia32_initreg(void) { | 
 |  |  | 
 | #if CPU_FAMILY == 4 | #if CPU_FAMILY == 4 | 
 | CPU_STATSAVE.cpu_regs.dr[6] = 0xffff1ff0; | CPU_STATSAVE.cpu_regs.dr[6] = 0xffff1ff0; | 
| #elif (CPU_FAMILY == 5) || (CPU_FAMILY == 6) | #elif CPU_FAMILY >= 5 | 
 | CPU_STATSAVE.cpu_regs.dr[6] = 0xffff0ff0; | CPU_STATSAVE.cpu_regs.dr[6] = 0xffff0ff0; | 
 | CPU_STATSAVE.cpu_regs.dr[7] = 0x00000400; | CPU_STATSAVE.cpu_regs.dr[7] = 0x00000400; | 
 | #endif | #endif | 
| Line 71  static void ia32_initreg(void) { | Line 74  static void ia32_initreg(void) { | 
 | CPU_SET_SEGREG(CPU_CS_INDEX, 0xf000); | CPU_SET_SEGREG(CPU_CS_INDEX, 0xf000); | 
 | CPU_EIP = 0xfff0; | CPU_EIP = 0xfff0; | 
 | CPU_ADRSMASK = 0x000fffff; | CPU_ADRSMASK = 0x000fffff; | 
 |  |  | 
 |  | tlb_init(); | 
 | } | } | 
 |  |  | 
 | void | void | 
| Line 112  ia32(void) | Line 117  ia32(void) | 
 | break; | break; | 
 | } | } | 
 |  |  | 
 |  | #if defined(IA32_SUPPORT_DEBUG_REGISTER) | 
 | do { | do { | 
 | exec_1step(); | exec_1step(); | 
| } while (CPU_REMCLOCK > 0); | if (dmac.working) { | 
| } | dmap(); | 
|  |  | 
| void |  | 
| ia32withtrap(void) |  | 
| { |  | 
| int rv; |  | 
|  |  | 
| rv = sigsetjmp(exec_1step_jmpbuf, 1); |  | 
| switch (rv) { |  | 
| case 0: |  | 
| break; |  | 
|  |  | 
| case 1: |  | 
| VERBOSE(("ia32withtrap: return from exception")); |  | 
| break; |  | 
|  |  | 
| case 2: |  | 
| VERBOSE(("ia32withtrap: return from panic")); |  | 
| return; |  | 
|  |  | 
| default: |  | 
| VERBOSE(("ia32withtrap: return from unknown cause")); |  | 
| break; |  | 
| } |  | 
|  |  | 
| do { |  | 
| exec_1step(); |  | 
| if (CPU_TRAP) { |  | 
| ia32_interrupt(1); |  | 
 | } | } | 
 | } while (CPU_REMCLOCK > 0); | } while (CPU_REMCLOCK > 0); | 
| } | #else | 
|  | if (CPU_TRAP) { | 
| void | do { | 
| ia32withdma(void) | exec_1step(); | 
| { | if (CPU_TRAP) { | 
| int rv; | CPU_DR6 |= CPU_DR6_BS; | 
|  | INTERRUPT(1, TRUE, FALSE, 0); | 
| rv = sigsetjmp(exec_1step_jmpbuf, 1); | } | 
| switch (rv) { | dmap(); | 
| case 0: | } while (CPU_REMCLOCK > 0); | 
| break; | } else if (dmac.working) { | 
|  | do { | 
| case 1: | exec_1step(); | 
| VERBOSE(("ia32withdma: return from exception")); | dmap(); | 
| break; | } while (CPU_REMCLOCK > 0); | 
|  | } else { | 
| case 2: | do { | 
| VERBOSE(("ia32withdma: return from panic")); | exec_1step(); | 
| return; | } while (CPU_REMCLOCK > 0); | 
|  |  | 
| default: |  | 
| VERBOSE(("ia32withdma: return from unknown cause")); |  | 
| break; |  | 
 | } | } | 
|  | #endif | 
| do { |  | 
| exec_1step(); |  | 
| dmap_i286(); |  | 
| } while (CPU_REMCLOCK > 0); |  | 
 | } | } | 
 |  |  | 
 | void | void | 
| Line 202  ia32_step(void) | Line 172  ia32_step(void) | 
 |  |  | 
 | do { | do { | 
 | exec_1step(); | exec_1step(); | 
 |  | #if !defined(IA32_SUPPORT_DEBUG_REGISTER) | 
 | if (CPU_TRAP) { | if (CPU_TRAP) { | 
| ia32_interrupt(1); | CPU_DR6 |= CPU_DR6_BS; | 
|  | INTERRUPT(1, TRUE, FALSE, 0); | 
|  | } | 
|  | #endif | 
|  | if (dmac.working) { | 
|  | dmap(); | 
 | } | } | 
 | dmap_i286(); |  | 
 | } while (CPU_REMCLOCK > 0); | } while (CPU_REMCLOCK > 0); | 
 | } | } | 
 |  |  | 
 | void CPUCALL | void CPUCALL | 
| ia32_interrupt(BYTE vect) | ia32_interrupt(int vect, int soft) | 
 | { | { | 
 |  |  | 
| INTERRUPT(vect, 0, 0, 0); | //      TRACEOUT(("int (%x, %x) PE=%d VM=%d",  vect, soft, CPU_STAT_PM, CPU_STAT_VM86)); | 
|  | if (!soft) { | 
|  | INTERRUPT(vect, FALSE, FALSE, 0); | 
|  | } | 
|  | else { | 
|  | if (CPU_STAT_VM86 && (CPU_STAT_IOPL < CPU_IOPL3) && (soft == -1)) { | 
|  | TRACEOUT(("BIOS interrupt: VM86 && IOPL < 3 && INTn")); | 
|  | } | 
|  | INTERRUPT(vect, TRUE, FALSE, 0); | 
|  | } | 
 | } | } | 
 |  |  | 
 |  |  | 
| Line 237  ia32_panic(const char *str, ...) | Line 221  ia32_panic(const char *str, ...) | 
 |  |  | 
 | #if defined(IA32_REBOOT_ON_PANIC) | #if defined(IA32_REBOOT_ON_PANIC) | 
 | VERBOSE(("ia32_panic: reboot")); | VERBOSE(("ia32_panic: reboot")); | 
 | pccore_cfgupdate(); |  | 
 | pccore_reset(); | pccore_reset(); | 
 | siglongjmp(exec_1step_jmpbuf, 2); | siglongjmp(exec_1step_jmpbuf, 2); | 
 | #else | #else | 
| Line 279  ia32_printf(const char *str, ...) | Line 262  ia32_printf(const char *str, ...) | 
 | void | void | 
 | ia32_bioscall(void) | ia32_bioscall(void) | 
 | { | { | 
| DWORD adrs; | UINT32 adrs; | 
 |  |  | 
 | if (!CPU_STAT_PM || CPU_STAT_VM86) { | if (!CPU_STAT_PM || CPU_STAT_VM86) { | 
| adrs = (CPU_EIP - 1) + CPU_STAT_SREGBASE(CPU_CS_INDEX); | #if 1 | 
|  | adrs = (CPU_EIP - 1) + ((CPU_REGS_SREG(CPU_CS_INDEX)) << 4); | 
|  | #else | 
|  | adrs = (CPU_EIP - 1) + CPU_STAT_CS_BASE; | 
|  | #endif | 
 | if ((adrs >= 0xf8000) && (adrs < 0x100000)) { | if ((adrs >= 0xf8000) && (adrs < 0x100000)) { | 
 | biosfunc(adrs); | biosfunc(adrs); | 
 | if (!CPU_STAT_PM || CPU_STAT_VM86) { | if (!CPU_STAT_PM || CPU_STAT_VM86) { |