|  | 
| version 1.16, 2004/03/06 18:25:36 | version 1.19, 2004/03/10 23:01:08 | 
|---|---|
| Line 60 ia32_initreg(void) | Line 60 ia32_initreg(void) | 
| #if CPU_FAMILY == 4 | #if CPU_FAMILY == 4 | 
| CPU_STATSAVE.cpu_regs.dr[6] = 0xffff1ff0; | CPU_STATSAVE.cpu_regs.dr[6] = 0xffff1ff0; | 
| #elif (CPU_FAMILY == 5) || (CPU_FAMILY == 6) | #elif CPU_FAMILY >= 5 | 
| CPU_STATSAVE.cpu_regs.dr[6] = 0xffff0ff0; | CPU_STATSAVE.cpu_regs.dr[6] = 0xffff0ff0; | 
| CPU_STATSAVE.cpu_regs.dr[7] = 0x00000400; | CPU_STATSAVE.cpu_regs.dr[7] = 0x00000400; | 
| #endif | #endif | 
| Line 117 ia32(void) | Line 117 ia32(void) | 
| break; | break; | 
| } | } | 
| #if defined(IA32_SUPPORT_DEBUG_REGISTER) | |
| do { | |
| exec_1step(); | |
| if (dmac.working) { | |
| dmap(); | |
| } | |
| } while (CPU_REMCLOCK > 0); | |
| #else | |
| if (CPU_TRAP) { | if (CPU_TRAP) { | 
| do { | do { | 
| exec_1step(); | exec_1step(); | 
| if (CPU_TRAP) { | if (CPU_TRAP) { | 
| ia32_interrupt(1); | CPU_DR6 |= CPU_DR6_BS; | 
| INTERRUPT(1, TRUE, FALSE, 0); | |
| } | } | 
| dmap(); | dmap(); | 
| } while (CPU_REMCLOCK > 0); | } while (CPU_REMCLOCK > 0); | 
| Line 135 ia32(void) | Line 144 ia32(void) | 
| exec_1step(); | exec_1step(); | 
| } while (CPU_REMCLOCK > 0); | } while (CPU_REMCLOCK > 0); | 
| } | } | 
| #endif | |
| } | } | 
| void | void | 
| Line 162 ia32_step(void) | Line 172 ia32_step(void) | 
| do { | do { | 
| exec_1step(); | exec_1step(); | 
| #if !defined(IA32_SUPPORT_DEBUG_REGISTER) | |
| if (CPU_TRAP) { | if (CPU_TRAP) { | 
| ia32_interrupt(1); | CPU_DR6 |= CPU_DR6_BS; | 
| INTERRUPT(1, TRUE, FALSE, 0); | |
| } | |
| #endif | |
| if (dmac.working) { | |
| dmap(); | |
| } | } | 
| dmap(); | |
| } while (CPU_REMCLOCK > 0); | } while (CPU_REMCLOCK > 0); | 
| } | } | 
| void CPUCALL | void CPUCALL | 
| ia32_interrupt(int vect) | ia32_interrupt(int vect, int soft) | 
| { | { | 
| INTERRUPT(vect, 0, 0, 0); | // TRACEOUT(("int (%x, %x) PE=%d VM=%d", vect, soft, CPU_STAT_PM, CPU_STAT_VM86)); | 
| if (!soft) { | |
| INTERRUPT(vect, FALSE, FALSE, 0); | |
| } | |
| else { | |
| if (CPU_STAT_VM86 && (CPU_STAT_IOPL < CPU_IOPL3) && (soft == -1)) { | |
| TRACEOUT(("BIOS interrupt: VM86 && IOPL < 3 && INTn")); | |
| } | |
| INTERRUPT(vect, TRUE, FALSE, 0); | |
| } | |
| } | } | 
| Line 197 ia32_panic(const char *str, ...) | Line 221 ia32_panic(const char *str, ...) | 
| #if defined(IA32_REBOOT_ON_PANIC) | #if defined(IA32_REBOOT_ON_PANIC) | 
| VERBOSE(("ia32_panic: reboot")); | VERBOSE(("ia32_panic: reboot")); | 
| pccore_cfgupdate(); | |
| pccore_reset(); | pccore_reset(); | 
| siglongjmp(exec_1step_jmpbuf, 2); | siglongjmp(exec_1step_jmpbuf, 2); | 
| #else | #else | 
| Line 242 ia32_bioscall(void) | Line 265 ia32_bioscall(void) | 
| UINT32 adrs; | UINT32 adrs; | 
| if (!CPU_STAT_PM || CPU_STAT_VM86) { | if (!CPU_STAT_PM || CPU_STAT_VM86) { | 
| #if 1 | |
| adrs = (CPU_EIP - 1) + ((CPU_REGS_SREG(CPU_CS_INDEX)) << 4); | |
| #else | |
| adrs = (CPU_EIP - 1) + CPU_STAT_CS_BASE; | adrs = (CPU_EIP - 1) + CPU_STAT_CS_BASE; | 
| #endif | |
| if ((adrs >= 0xf8000) && (adrs < 0x100000)) { | if ((adrs >= 0xf8000) && (adrs < 0x100000)) { | 
| biosfunc(adrs); | biosfunc(adrs); | 
| if (!CPU_STAT_PM || CPU_STAT_VM86) { | if (!CPU_STAT_PM || CPU_STAT_VM86) { |