| version 1.19, 2004/03/10 23:01:08 | version 1.23, 2005/03/05 16:47:04 | 
| Line 30 | Line 30 | 
 | #include "compiler.h" | #include "compiler.h" | 
 | #include "cpu.h" | #include "cpu.h" | 
 | #include "ia32.mcr" | #include "ia32.mcr" | 
 |  | #if defined(USE_FPU) | 
 |  | #include "instructions/fpu/fp.h" | 
 |  | #endif | 
 |  |  | 
 | #include "pccore.h" | #include "pccore.h" | 
 | #include "iocore.h" | #include "iocore.h" | 
| #include "dmap.h" | #include "dmax86.h" | 
 | #include "bios.h" | #include "bios.h" | 
 | #if defined(IA32_REBOOT_ON_PANIC) | #if defined(IA32_REBOOT_ON_PANIC) | 
 | #include "pccore.h" | #include "pccore.h" | 
| Line 50  ia32_initreg(void) | Line 53  ia32_initreg(void) | 
 | CPU_EDX = (CPU_FAMILY << 8) | (CPU_MODEL << 4) | CPU_STEPPING; | CPU_EDX = (CPU_FAMILY << 8) | (CPU_MODEL << 4) | CPU_STEPPING; | 
 | CPU_EFLAG = 2; | CPU_EFLAG = 2; | 
 | CPU_CR0 = CPU_CR0_CD | CPU_CR0_NW | CPU_CR0_ET; | CPU_CR0 = CPU_CR0_CD | CPU_CR0_NW | CPU_CR0_ET; | 
| #ifndef USE_FPU | #if defined(USE_FPU) | 
 | CPU_CR0 |= CPU_CR0_EM | CPU_CR0_NE; | CPU_CR0 |= CPU_CR0_EM | CPU_CR0_NE; | 
 | CPU_CR0 &= ~CPU_CR0_MP; | CPU_CR0 &= ~CPU_CR0_MP; | 
 |  | #else | 
 |  | CPU_CR0 |= CPU_CR0_ET; | 
 | #endif | #endif | 
 | CPU_MXCSR = 0x1f80; | CPU_MXCSR = 0x1f80; | 
 | CPU_GDTR_LIMIT = 0xffff; | CPU_GDTR_LIMIT = 0xffff; | 
| Line 76  ia32_initreg(void) | Line 81  ia32_initreg(void) | 
 | CPU_ADRSMASK = 0x000fffff; | CPU_ADRSMASK = 0x000fffff; | 
 |  |  | 
 | tlb_init(); | tlb_init(); | 
 |  | #if defined(USE_FPU) | 
 |  | fpu_init(); | 
 |  | #endif | 
 | } | } | 
 |  |  | 
 | void | void | 
| Line 95  ia32shut(void) | Line 103  ia32shut(void) | 
 | } | } | 
 |  |  | 
 | void | void | 
 |  | ia32a20enable(BOOL enable) | 
 |  | { | 
 |  | #if (CPU_FAMILY == 3) | 
 |  | CPU_ADRSMASK = (enable)?0x00ffffff:0x00ffffff; | 
 |  | #else | 
 |  | CPU_ADRSMASK = (enable)?0xffffffff:0x00ffffff; | 
 |  | #endif | 
 |  | } | 
 |  |  | 
 |  | void | 
 | ia32(void) | ia32(void) | 
 | { | { | 
 | int rv; | int rv; | 
| Line 121  ia32(void) | Line 139  ia32(void) | 
 | do { | do { | 
 | exec_1step(); | exec_1step(); | 
 | if (dmac.working) { | if (dmac.working) { | 
| dmap(); | dmax86(); | 
 | } | } | 
 | } while (CPU_REMCLOCK > 0); | } while (CPU_REMCLOCK > 0); | 
 | #else | #else | 
| Line 132  ia32(void) | Line 150  ia32(void) | 
 | CPU_DR6 |= CPU_DR6_BS; | CPU_DR6 |= CPU_DR6_BS; | 
 | INTERRUPT(1, TRUE, FALSE, 0); | INTERRUPT(1, TRUE, FALSE, 0); | 
 | } | } | 
| dmap(); | dmax86(); | 
 | } while (CPU_REMCLOCK > 0); | } while (CPU_REMCLOCK > 0); | 
 | } else if (dmac.working) { | } else if (dmac.working) { | 
 | do { | do { | 
 | exec_1step(); | exec_1step(); | 
| dmap(); | dmax86(); | 
 | } while (CPU_REMCLOCK > 0); | } while (CPU_REMCLOCK > 0); | 
 | } else { | } else { | 
 | do { | do { | 
| Line 179  ia32_step(void) | Line 197  ia32_step(void) | 
 | } | } | 
 | #endif | #endif | 
 | if (dmac.working) { | if (dmac.working) { | 
| dmap(); | dmax86(); | 
 | } | } | 
 | } while (CPU_REMCLOCK > 0); | } while (CPU_REMCLOCK > 0); | 
 | } | } | 
| Line 271  ia32_bioscall(void) | Line 289  ia32_bioscall(void) | 
 | adrs = (CPU_EIP - 1) + CPU_STAT_CS_BASE; | adrs = (CPU_EIP - 1) + CPU_STAT_CS_BASE; | 
 | #endif | #endif | 
 | if ((adrs >= 0xf8000) && (adrs < 0x100000)) { | if ((adrs >= 0xf8000) && (adrs < 0x100000)) { | 
| biosfunc(adrs); | if (biosfunc(adrs)) { | 
|  | CPU_PREFETCH_CLEAR(); | 
|  | } | 
 | if (!CPU_STAT_PM || CPU_STAT_VM86) { | if (!CPU_STAT_PM || CPU_STAT_VM86) { | 
 | CPU_SET_SEGREG(CPU_ES_INDEX, CPU_ES); | CPU_SET_SEGREG(CPU_ES_INDEX, CPU_ES); | 
 | CPU_SET_SEGREG(CPU_CS_INDEX, CPU_CS); | CPU_SET_SEGREG(CPU_CS_INDEX, CPU_CS); |