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Diff for /np2/i386c/ia32/interface.c between versions 1.21 and 1.24

version 1.21, 2004/05/23 15:01:45 version 1.24, 2005/03/12 12:32:54
Line 12 Line 12
  * 2. Redistributions in binary form must reproduce the above copyright   * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the   *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.   *    documentation and/or other materials provided with the distribution.
  * 3. The name of the author may not be used to endorse or promote products  
  *    derived from this software without specific prior written permission.  
  *   *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR   * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES   * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
Line 30 Line 28
 #include "compiler.h"  #include "compiler.h"
 #include "cpu.h"  #include "cpu.h"
 #include "ia32.mcr"  #include "ia32.mcr"
   #if defined(USE_FPU)
   #include "instructions/fpu/fp.h"
   #endif
   
 #include "pccore.h"  #include "pccore.h"
 #include "iocore.h"  #include "iocore.h"
 #include "dmap.h"  #include "dmax86.h"
 #include "bios.h"  #include "bios.h"
 #if defined(IA32_REBOOT_ON_PANIC)  #if defined(IA32_REBOOT_ON_PANIC)
 #include "pccore.h"  #include "pccore.h"
Line 50  ia32_initreg(void) Line 51  ia32_initreg(void)
         CPU_EDX = (CPU_FAMILY << 8) | (CPU_MODEL << 4) | CPU_STEPPING;          CPU_EDX = (CPU_FAMILY << 8) | (CPU_MODEL << 4) | CPU_STEPPING;
         CPU_EFLAG = 2;          CPU_EFLAG = 2;
         CPU_CR0 = CPU_CR0_CD | CPU_CR0_NW | CPU_CR0_ET;          CPU_CR0 = CPU_CR0_CD | CPU_CR0_NW | CPU_CR0_ET;
 #ifndef USE_FPU  #if defined(USE_FPU)
         CPU_CR0 |= CPU_CR0_EM | CPU_CR0_NE;          CPU_CR0 |= CPU_CR0_EM | CPU_CR0_NE;
         CPU_CR0 &= ~CPU_CR0_MP;          CPU_CR0 &= ~CPU_CR0_MP;
   #else
           CPU_CR0 |= CPU_CR0_ET;
 #endif  #endif
         CPU_MXCSR = 0x1f80;          CPU_MXCSR = 0x1f80;
         CPU_GDTR_LIMIT = 0xffff;          CPU_GDTR_LIMIT = 0xffff;
Line 76  ia32_initreg(void) Line 79  ia32_initreg(void)
         CPU_ADRSMASK = 0x000fffff;          CPU_ADRSMASK = 0x000fffff;
   
         tlb_init();          tlb_init();
   #if defined(USE_FPU)
           fpu_init();
   #endif
 }  }
   
 void  void
Line 131  ia32(void) Line 137  ia32(void)
         do {          do {
                 exec_1step();                  exec_1step();
                 if (dmac.working) {                  if (dmac.working) {
                         dmap();                          dmax86();
                 }                  }
         } while (CPU_REMCLOCK > 0);          } while (CPU_REMCLOCK > 0);
 #else  #else
Line 142  ia32(void) Line 148  ia32(void)
                                 CPU_DR6 |= CPU_DR6_BS;                                  CPU_DR6 |= CPU_DR6_BS;
                                 INTERRUPT(1, TRUE, FALSE, 0);                                  INTERRUPT(1, TRUE, FALSE, 0);
                         }                          }
                         dmap();                          dmax86();
                 } while (CPU_REMCLOCK > 0);                  } while (CPU_REMCLOCK > 0);
         } else if (dmac.working) {          } else if (dmac.working) {
                 do {                  do {
                         exec_1step();                          exec_1step();
                         dmap();                          dmax86();
                 } while (CPU_REMCLOCK > 0);                  } while (CPU_REMCLOCK > 0);
         } else {          } else {
                 do {                  do {
Line 189  ia32_step(void) Line 195  ia32_step(void)
                 }                  }
 #endif  #endif
                 if (dmac.working) {                  if (dmac.working) {
                         dmap();                          dmax86();
                 }                  }
         } while (CPU_REMCLOCK > 0);          } while (CPU_REMCLOCK > 0);
 }  }
Removed from v.1.21  
changed lines
  Added in v.1.24

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