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| version 1.22, 2005/02/08 09:57:26 | version 1.23, 2005/03/05 16:47:04 |
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| Line 30 | Line 30 |
| #include "compiler.h" | #include "compiler.h" |
| #include "cpu.h" | #include "cpu.h" |
| #include "ia32.mcr" | #include "ia32.mcr" |
| #if defined(USE_FPU) | |
| #include "instructions/fpu/fp.h" | |
| #endif | |
| #include "pccore.h" | #include "pccore.h" |
| #include "iocore.h" | #include "iocore.h" |
| Line 50 ia32_initreg(void) | Line 53 ia32_initreg(void) |
| CPU_EDX = (CPU_FAMILY << 8) | (CPU_MODEL << 4) | CPU_STEPPING; | CPU_EDX = (CPU_FAMILY << 8) | (CPU_MODEL << 4) | CPU_STEPPING; |
| CPU_EFLAG = 2; | CPU_EFLAG = 2; |
| CPU_CR0 = CPU_CR0_CD | CPU_CR0_NW | CPU_CR0_ET; | CPU_CR0 = CPU_CR0_CD | CPU_CR0_NW | CPU_CR0_ET; |
| #ifndef USE_FPU | #if defined(USE_FPU) |
| CPU_CR0 |= CPU_CR0_EM | CPU_CR0_NE; | CPU_CR0 |= CPU_CR0_EM | CPU_CR0_NE; |
| CPU_CR0 &= ~CPU_CR0_MP; | CPU_CR0 &= ~CPU_CR0_MP; |
| #else | |
| CPU_CR0 |= CPU_CR0_ET; | |
| #endif | #endif |
| CPU_MXCSR = 0x1f80; | CPU_MXCSR = 0x1f80; |
| CPU_GDTR_LIMIT = 0xffff; | CPU_GDTR_LIMIT = 0xffff; |
| Line 76 ia32_initreg(void) | Line 81 ia32_initreg(void) |
| CPU_ADRSMASK = 0x000fffff; | CPU_ADRSMASK = 0x000fffff; |
| tlb_init(); | tlb_init(); |
| #if defined(USE_FPU) | |
| fpu_init(); | |
| #endif | |
| } | } |
| void | void |