np2/i386c/ia32/interface.c - diff

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Diff for /np2/i386c/ia32/interface.c between versions 1.3 and 1.7

version 1.3, 2003/12/25 19:21:17	version 1.7, 2004/01/23 14:33:26
Line 30	Line 30
#include "compiler.h"	#include "compiler.h"
#include "cpu.h"	#include "cpu.h"
#include "ia32.mcr"	#include "ia32.mcr"

#include "dmap.h"	#include "dmap.h"
#include "bios.h"	#include "bios.h"

Line 39 ia32reset(void)	Line 40 ia32reset(void)
{	{
int i;	int i;

memset(&i386core.s, 0, sizeof(i386core.s)); // yui	memset(&i386core.s, 0, sizeof(i386core.s));
CPU_STATSAVE.cpu_inst_default.seg_base = (DWORD)-1;	CPU_STATSAVE.cpu_inst_default.seg_base = (DWORD)-1;

CPU_EDX = (CPU_FAMILY << 8) \| (CPU_MODEL << 4) \| CPU_STEPPING;	CPU_EDX = (CPU_FAMILY << 8) \| (CPU_MODEL << 4) \| CPU_STEPPING;
CPU_EFLAG = 2;	CPU_EFLAG = 2;
CPU_CR0 = CPU_CR0_CD \| CPU_CR0_NW \| CPU_CR0_ET;	CPU_CR0 = CPU_CR0_CD \| CPU_CR0_NW \| CPU_CR0_ET;
	#ifndef USE_FPU
	CPU_CR0 \|= CPU_CR0_EM \| CPU_CR0_NE;
	CPU_CR0 &= ~CPU_CR0_MP;
	#endif
CPU_MXCSR = 0x1f80;	CPU_MXCSR = 0x1f80;
CPU_GDTR_LIMIT = 0xffff;	CPU_GDTR_LIMIT = 0xffff;
CPU_IDTR_LIMIT = 0xffff;	CPU_IDTR_LIMIT = 0xffff;

	#if CPU_FAMILY == 4
	CPU_STATSAVE.cpu_regs.dr[6] = 0xffff1ff0;
	#elif (CPU_FAMILY == 5) \|\| (CPU_FAMILY == 6)
	CPU_STATSAVE.cpu_regs.dr[6] = 0xffff0ff0;
	CPU_STATSAVE.cpu_regs.dr[7] = 0x00000400;
	#endif

for (i = 0; i < CPU_SEGREG_NUM; ++i) {	for (i = 0; i < CPU_SEGREG_NUM; ++i) {
CPU_STAT_SREG_INIT(i);	CPU_STAT_SREG_INIT(i);
}	}
CPU_LDTR_LIMIT = 0xffff;	CPU_LDTR_LIMIT = 0xffff;
CPU_TR_LIMIT = 0xffff;	CPU_TR_LIMIT = 0xffff;

CPU_SET_SEGREG(CPU_CS_INDEX, 0xffff);	CPU_SET_SEGREG(CPU_CS_INDEX, 0xf000);
CPU_ADRSMASK = 0xfffff;	CPU_EIP = 0xfff0;
// CPU_EIP = 0;	CPU_ADRSMASK = 0x000fffff;
}	}

void	void
ia32shut(void)	ia32shut(void)
{	{
SINT32 remainclock; // 結局ハマるのか漏れ…	SINT32 remainclock; /* 結局ハマるのか漏れ… */
SINT32 baseclock;	SINT32 baseclock;
UINT32 clock;	UINT32 clock;

Line 83 ia32(void)	Line 95 ia32(void)
{	{
int rv;	int rv;

#if defined(WIN32)
rv = setjmp(exec_1step_jmpbuf);
#else
rv = sigsetjmp(exec_1step_jmpbuf, 1);	rv = sigsetjmp(exec_1step_jmpbuf, 1);
#endif
switch (rv) {	switch (rv) {
case 0:	case 0:
break;	break;

	case 1:
	VERBOSE(("ia32: return from exception"));
	break;

default:	default:
CPU_EIP = CPU_PREV_EIP;	VERBOSE(("ia32: return from unknown cause"));
break;	break;
}	}

Line 107 ia32withtrap(void)	Line 119 ia32withtrap(void)
{	{
int rv;	int rv;

#if defined(WIN32)
rv = setjmp(exec_1step_jmpbuf);
#else
rv = sigsetjmp(exec_1step_jmpbuf, 1);	rv = sigsetjmp(exec_1step_jmpbuf, 1);
#endif
switch (rv) {	switch (rv) {
case 0:	case 0:
break;	break;

	case 1:
	VERBOSE(("ia32withtrap: return from exception"));
	break;

default:	default:
CPU_EIP = CPU_PREV_EIP;	VERBOSE(("ia32withtrap: return from unknown cause"));
break;	break;
}	}


do {	do {
exec_1step();	exec_1step();
if (CPU_TRAP) {	if (CPU_TRAP) {
Line 135 ia32withdma(void)	Line 146 ia32withdma(void)
{	{
int rv;	int rv;

#if defined(WIN32)
rv = setjmp(exec_1step_jmpbuf);
#else
rv = sigsetjmp(exec_1step_jmpbuf, 1);	rv = sigsetjmp(exec_1step_jmpbuf, 1);
#endif
switch (rv) {	switch (rv) {
case 0:	case 0:
break;	break;

	case 1:
	VERBOSE(("ia32withdma: return from exception"));
	break;

default:	default:
CPU_EIP = CPU_PREV_EIP;	VERBOSE(("ia32withdma: return from unknown cause"));
break;	break;
}	}


do {	do {
exec_1step();	exec_1step();
dmap_i286();	dmap_i286();
Line 161 ia32_step(void)	Line 171 ia32_step(void)
{	{
int rv;	int rv;

#if defined(WIN32)
rv = setjmp(exec_1step_jmpbuf);
#else
rv = sigsetjmp(exec_1step_jmpbuf, 1);	rv = sigsetjmp(exec_1step_jmpbuf, 1);
#endif
switch (rv) {	switch (rv) {
case 0:	case 0:
break;	break;

	case 1:
	VERBOSE(("ia32_step: return from exception"));
	break;

default:	default:
CPU_EIP = CPU_PREV_EIP;	VERBOSE(("ia32_step: return from unknown cause"));
break;	break;
}	}


do {	do {
exec_1step();	exec_1step();
if (CPU_TRAP) {	if (CPU_TRAP) {
Line 192 ia32_interrupt(BYTE vect)	Line 201 ia32_interrupt(BYTE vect)
INTERRUPT(vect, 0, 0, 0);	INTERRUPT(vect, 0, 0, 0);
}	}


/*	/*
* error function	* error function
*/	*/
void	void
ia32_panic(const char *str, ...)	ia32_panic(const char *str, ...)
{	{
char buf[1024];	extern char *cpu_reg2str(void);
	char buf[2048];
va_list ap;	va_list ap;

va_start(ap, str);	va_start(ap, str);
vsnprintf(buf, sizeof(buf), str, ap);	vsnprintf(buf, sizeof(buf), str, ap);
va_end(ap);	va_end(ap);
strcat(buf, "\n");	strcat(buf, "\n");
	strcat(buf, cpu_reg2str());

	msgbox("ia32_panic", buf);

fprintf(stderr, buf);
__ASSERT(0);	__ASSERT(0);
exit(1);	exit(1);
}	}
Line 220 ia32_warning(const char *str, ...)	Line 234 ia32_warning(const char *str, ...)
va_end(ap);	va_end(ap);
strcat(buf, "\n");	strcat(buf, "\n");

fprintf(stderr, buf);	msgbox("ia32_warning", buf);
}	}

void	void
Line 231 ia32_printf(const char *str, ...)	Line 245 ia32_printf(const char *str, ...)
va_start(ap, str);	va_start(ap, str);
vsnprintf(buf, sizeof(buf), str, ap);	vsnprintf(buf, sizeof(buf), str, ap);
va_end(ap);	va_end(ap);
	strcat(buf, "\n");

fprintf(stderr, buf);	msgbox("ia32_printf", buf);
}	}


/*	/*
* bios call interface	* bios call interface
*/	*/
void	void
ia32_bioscall(void)	ia32_bioscall(void)
{	{
	DWORD adrs;

/* XXX */
if (!CPU_STAT_PM && !CPU_INST_OP32 && !CPU_INST_AS32) {	if (!CPU_STAT_PM && !CPU_INST_OP32 && !CPU_INST_AS32) {
DWORD adrs;
WORD sreg;

adrs = ((CPU_IP-1) & 0xffff) + CPU_STAT_SREGBASE(CPU_CS_INDEX);	adrs = ((CPU_IP-1) & 0xffff) + CPU_STAT_SREGBASE(CPU_CS_INDEX);
if ((adrs >= 0xf8000) && (adrs < 0x100000)) {	if ((adrs >= 0xf8000) && (adrs < 0x100000)) {
biosfunc(adrs);	biosfunc(adrs);
sreg = CPU_ES;	CPU_SET_SEGREG(CPU_ES_INDEX, CPU_ES);
CPU_SET_SEGREG(CPU_ES_INDEX, sreg);	CPU_SET_SEGREG(CPU_CS_INDEX, CPU_CS);
sreg = CPU_CS;	CPU_SET_SEGREG(CPU_SS_INDEX, CPU_SS);
CPU_SET_SEGREG(CPU_CS_INDEX, sreg);	CPU_SET_SEGREG(CPU_DS_INDEX, CPU_DS);
sreg = CPU_SS;
CPU_SET_SEGREG(CPU_SS_INDEX, sreg);
sreg = CPU_DS;
CPU_SET_SEGREG(CPU_DS_INDEX, sreg);
}	}
}	}
}	}

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