np2/i386c/ia32/interface.c - diff

Return to interface.c CVS log

Up to [RetroPC.NET] / np2 / i386c / ia32

Diff for /np2/i386c/ia32/interface.c between versions 1.7 and 1.30

version 1.7, 2004/01/23 14:33:26	version 1.30, 2011/12/20 02:00:32
Line 1	Line 1
/* $Id$ */

/*	/*
* Copyright (c) 2002-2003 NONAKA Kimihiro	* Copyright (c) 2002-2003 NONAKA Kimihiro
* All rights reserved.	* All rights reserved.
Line 12	Line 10
* 2. Redistributions in binary form must reproduce the above copyright	* 2. Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the	* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.	* documentation and/or other materials provided with the distribution.
* 3. The name of the author may not be used to endorse or promote products
* derived from this software without specific prior written permission.
*	*
* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR	* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES	* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
Line 30	Line 26
#include "compiler.h"	#include "compiler.h"
#include "cpu.h"	#include "cpu.h"
#include "ia32.mcr"	#include "ia32.mcr"
	#if defined(USE_FPU)
	#include "instructions/fpu/fp.h"
	#endif

#include "dmap.h"	#include "pccore.h"
	#include "iocore.h"
	#include "dmax86.h"
#include "bios.h"	#include "bios.h"


void	void
ia32reset(void)	ia32_initreg(void)
{	{
int i;	int i;

memset(&i386core.s, 0, sizeof(i386core.s));	CPU_STATSAVE.cpu_inst_default.seg_base = (UINT32)-1;
CPU_STATSAVE.cpu_inst_default.seg_base = (DWORD)-1;

CPU_EDX = (CPU_FAMILY << 8) \| (CPU_MODEL << 4) \| CPU_STEPPING;	CPU_EDX = (CPU_FAMILY << 8) \| (CPU_MODEL << 4) \| CPU_STEPPING;
CPU_EFLAG = 2;	CPU_EFLAG = 2;
CPU_CR0 = CPU_CR0_CD \| CPU_CR0_NW \| CPU_CR0_ET;	CPU_CR0 = CPU_CR0_CD \| CPU_CR0_NW \| CPU_CR0_ET;
#ifndef USE_FPU	#if defined(USE_FPU)
	CPU_CR0 \|= CPU_CR0_ET;
	#else
CPU_CR0 \|= CPU_CR0_EM \| CPU_CR0_NE;	CPU_CR0 \|= CPU_CR0_EM \| CPU_CR0_NE;
CPU_CR0 &= ~CPU_CR0_MP;	CPU_CR0 &= ~(CPU_CR0_MP \| CPU_CR0_ET);
#endif	#endif
CPU_MXCSR = 0x1f80;	CPU_MXCSR = 0x1f80;

	CPU_GDTR_BASE = 0x0;
CPU_GDTR_LIMIT = 0xffff;	CPU_GDTR_LIMIT = 0xffff;
	CPU_IDTR_BASE = 0x0;
CPU_IDTR_LIMIT = 0xffff;	CPU_IDTR_LIMIT = 0xffff;
	CPU_LDTR_BASE = 0x0;
	CPU_LDTR_LIMIT = 0xffff;
	CPU_TR_BASE = 0x0;
	CPU_TR_LIMIT = 0xffff;

#if CPU_FAMILY == 4
CPU_STATSAVE.cpu_regs.dr[6] = 0xffff1ff0;	CPU_STATSAVE.cpu_regs.dr[6] = 0xffff1ff0;
#elif (CPU_FAMILY == 5) \|\| (CPU_FAMILY == 6)
CPU_STATSAVE.cpu_regs.dr[6] = 0xffff0ff0;
CPU_STATSAVE.cpu_regs.dr[7] = 0x00000400;
#endif

for (i = 0; i < CPU_SEGREG_NUM; ++i) {	for (i = 0; i < CPU_SEGREG_NUM; ++i) {
CPU_STAT_SREG_INIT(i);	segdesc_init(i, 0, &CPU_STAT_SREG(i));
}	}
CPU_LDTR_LIMIT = 0xffff;	LOAD_SEGREG(CPU_CS_INDEX, 0xf000);
CPU_TR_LIMIT = 0xffff;	CPU_STAT_CS_BASE = 0xffff0000;

CPU_SET_SEGREG(CPU_CS_INDEX, 0xf000);
CPU_EIP = 0xfff0;	CPU_EIP = 0xfff0;
CPU_ADRSMASK = 0x000fffff;	CPU_ADRSMASK = 0x000fffff;

	tlb_init();
	#if defined(USE_FPU)
	fpu_init();
	#endif
}	}

void	void
ia32shut(void)	ia32reset(void)
{	{
SINT32 remainclock; /* 結局ハマるのか漏れ… */
SINT32 baseclock;	memset(&i386core.s, 0, sizeof(i386core.s));
UINT32 clock;	ia32_initreg();

remainclock = CPU_REMCLOCK;
baseclock = CPU_BASECLOCK;
clock = CPU_CLOCK;

ia32reset();

CPU_REMCLOCK = remainclock;
CPU_BASECLOCK = baseclock;
CPU_CLOCK = clock;
}	}

void	void
ia32(void)	ia32shut(void)
{	{
int rv;

rv = sigsetjmp(exec_1step_jmpbuf, 1);	memset(&i386core.s, 0, offsetof(I386STAT, cpu_type));
switch (rv) {	ia32_initreg();
case 0:
break;

case 1:
VERBOSE(("ia32: return from exception"));
break;

default:
VERBOSE(("ia32: return from unknown cause"));
break;
}

do {
exec_1step();
} while (CPU_REMCLOCK > 0);
}	}

void	void
ia32withtrap(void)	ia32a20enable(BOOL enable)
{	{
int rv;

rv = sigsetjmp(exec_1step_jmpbuf, 1);	CPU_ADRSMASK = (enable)?0xffffffff:0x00ffffff;
switch (rv) {
case 0:
break;

case 1:
VERBOSE(("ia32withtrap: return from exception"));
break;

default:
VERBOSE(("ia32withtrap: return from unknown cause"));
break;
}

do {
exec_1step();
if (CPU_TRAP) {
ia32_interrupt(1);
}
} while (CPU_REMCLOCK > 0);
}	}

void	void
ia32withdma(void)	ia32(void)
{	{
int rv;	int rv;

Line 152 ia32withdma(void)	Line 113 ia32withdma(void)
break;	break;

case 1:	case 1:
VERBOSE(("ia32withdma: return from exception"));	VERBOSE(("ia32: return from exception"));
break;	break;

	case 2:
	VERBOSE(("ia32: return from panic"));
	return;

default:	default:
VERBOSE(("ia32withdma: return from unknown cause"));	VERBOSE(("ia32: return from unknown cause"));
break;	break;
}	}

	#if defined(IA32_SUPPORT_DEBUG_REGISTER)
do {	do {
exec_1step();	exec_1step();
dmap_i286();	if (dmac.working) {
	dmax86();
	}
} while (CPU_REMCLOCK > 0);	} while (CPU_REMCLOCK > 0);
	#else
	if (CPU_TRAP) {
	do {
	exec_1step();
	if (CPU_TRAP) {
	CPU_DR6 \|= CPU_DR6_BS;
	INTERRUPT(1, INTR_TYPE_EXCEPTION);
	}
	dmax86();
	} while (CPU_REMCLOCK > 0);
	} else if (dmac.working) {
	do {
	exec_1step();
	dmax86();
	} while (CPU_REMCLOCK > 0);
	} else {
	do {
	exec_1step();
	} while (CPU_REMCLOCK > 0);
	}
	#endif
}	}

void	void
Line 180 ia32_step(void)	Line 169 ia32_step(void)
VERBOSE(("ia32_step: return from exception"));	VERBOSE(("ia32_step: return from exception"));
break;	break;

	case 2:
	VERBOSE(("ia32_step: return from panic"));
	return;

default:	default:
VERBOSE(("ia32_step: return from unknown cause"));	VERBOSE(("ia32_step: return from unknown cause"));
break;	break;
Line 187 ia32_step(void)	Line 180 ia32_step(void)

do {	do {
exec_1step();	exec_1step();
	#if !defined(IA32_SUPPORT_DEBUG_REGISTER)
if (CPU_TRAP) {	if (CPU_TRAP) {
ia32_interrupt(1);	CPU_DR6 \|= CPU_DR6_BS;
	INTERRUPT(1, INTR_TYPE_EXCEPTION);
	}
	#endif
	if (dmac.working) {
	dmax86();
}	}
dmap_i286();
} while (CPU_REMCLOCK > 0);	} while (CPU_REMCLOCK > 0);
}	}

void CPUCALL	void CPUCALL
ia32_interrupt(BYTE vect)	ia32_interrupt(int vect, int soft)
{	{

INTERRUPT(vect, 0, 0, 0);	// TRACEOUT(("int (%x, %x) PE=%d VM=%d", vect, soft, CPU_STAT_PM, CPU_STAT_VM86));
	if (!soft) {
	INTERRUPT(vect, INTR_TYPE_EXTINTR);
	} else {
	if (CPU_STAT_PM && CPU_STAT_VM86 && CPU_STAT_IOPL < CPU_IOPL3) {
	VERBOSE(("ia32_interrupt: VM86 && IOPL < 3 && INTn"));
	EXCEPTION(GP_EXCEPTION, 0);
	}
	INTERRUPT(vect, INTR_TYPE_SOFTINTR);
	}
}	}


Line 220 ia32_panic(const char *str, ...)	Line 227 ia32_panic(const char *str, ...)

msgbox("ia32_panic", buf);	msgbox("ia32_panic", buf);

	#if defined(IA32_REBOOT_ON_PANIC)
	VERBOSE(("ia32_panic: reboot"));
	pccore_reset();
	siglongjmp(exec_1step_jmpbuf, 2);
	#else
__ASSERT(0);	__ASSERT(0);
exit(1);	exit(1);
	#endif
}	}

void	void
Line 257 ia32_printf(const char *str, ...)	Line 270 ia32_printf(const char *str, ...)
void	void
ia32_bioscall(void)	ia32_bioscall(void)
{	{
DWORD adrs;	UINT32 adrs;

if (!CPU_STAT_PM && !CPU_INST_OP32 && !CPU_INST_AS32) {	if (!CPU_STAT_PM \|\| CPU_STAT_VM86) {
adrs = ((CPU_IP-1) & 0xffff) + CPU_STAT_SREGBASE(CPU_CS_INDEX);	#if 1
	adrs = CPU_PREV_EIP + (CPU_CS << 4);
	#else
	adrs = CPU_PREV_EIP + CPU_STAT_CS_BASE;
	#endif
if ((adrs >= 0xf8000) && (adrs < 0x100000)) {	if ((adrs >= 0xf8000) && (adrs < 0x100000)) {
biosfunc(adrs);	if (biosfunc(adrs)) {
CPU_SET_SEGREG(CPU_ES_INDEX, CPU_ES);	/* Nothing to do */
CPU_SET_SEGREG(CPU_CS_INDEX, CPU_CS);	}
CPU_SET_SEGREG(CPU_SS_INDEX, CPU_SS);	LOAD_SEGREG(CPU_ES_INDEX, CPU_ES);
CPU_SET_SEGREG(CPU_DS_INDEX, CPU_DS);	LOAD_SEGREG(CPU_CS_INDEX, CPU_CS);
	LOAD_SEGREG(CPU_SS_INDEX, CPU_SS);
	LOAD_SEGREG(CPU_DS_INDEX, CPU_DS);
}	}
}	}
}	}

RetroPC.NET-CVS <cvs@retropc.net>

Removed from v.1.7
changed lines
	Added in v.1.30