| version 1.27, 2008/03/22 04:03:07 | version 1.33, 2012/01/24 17:17:12 | 
| Line 1 | Line 1 | 
 | /*      $Id$    */ |  | 
 |  |  | 
 | /* | /* | 
 | * Copyright (c) 2002-2003 NONAKA Kimihiro | * Copyright (c) 2002-2003 NONAKA Kimihiro | 
 | * All rights reserved. | * All rights reserved. | 
| Line 36 | Line 34 | 
 | #include "iocore.h" | #include "iocore.h" | 
 | #include "dmax86.h" | #include "dmax86.h" | 
 | #include "bios.h" | #include "bios.h" | 
 | #if defined(IA32_REBOOT_ON_PANIC) |  | 
 | #include "pccore.h" |  | 
 | #endif |  | 
 |  |  | 
 |  |  | 
 | void | void | 
| Line 50  ia32_initreg(void) | Line 45  ia32_initreg(void) | 
 |  |  | 
 | CPU_EDX = (CPU_FAMILY << 8) | (CPU_MODEL << 4) | CPU_STEPPING; | CPU_EDX = (CPU_FAMILY << 8) | (CPU_MODEL << 4) | CPU_STEPPING; | 
 | CPU_EFLAG = 2; | CPU_EFLAG = 2; | 
| CPU_CR0 = CPU_CR0_CD | CPU_CR0_NW | CPU_CR0_ET; | CPU_CR0 = CPU_CR0_CD | CPU_CR0_NW; | 
 | #if defined(USE_FPU) | #if defined(USE_FPU) | 
| CPU_CR0 |= CPU_CR0_EM | CPU_CR0_NE; | CPU_CR0 &= ~CPU_CR0_EM; | 
| CPU_CR0 &= ~CPU_CR0_MP; |  | 
| #else |  | 
 | CPU_CR0 |= CPU_CR0_ET; | CPU_CR0 |= CPU_CR0_ET; | 
 |  | #else | 
 |  | CPU_CR0 |= CPU_CR0_EM | CPU_CR0_NE; | 
 |  | CPU_CR0 &= ~(CPU_CR0_MP | CPU_CR0_ET); | 
 | #endif | #endif | 
 | CPU_MXCSR = 0x1f80; | CPU_MXCSR = 0x1f80; | 
 |  |  | 
| Line 130  ia32(void) | Line 126  ia32(void) | 
 | break; | break; | 
 | } | } | 
 |  |  | 
 | #if defined(IA32_SUPPORT_DEBUG_REGISTER) |  | 
 | do { |  | 
 | exec_1step(); |  | 
 | if (dmac.working) { |  | 
 | dmax86(); |  | 
 | } |  | 
 | } while (CPU_REMCLOCK > 0); |  | 
 | #else |  | 
 | if (CPU_TRAP) { | if (CPU_TRAP) { | 
 | do { | do { | 
 | exec_1step(); | exec_1step(); | 
| Line 157  ia32(void) | Line 145  ia32(void) | 
 | exec_1step(); | exec_1step(); | 
 | } while (CPU_REMCLOCK > 0); | } while (CPU_REMCLOCK > 0); | 
 | } | } | 
 | #endif |  | 
 | } | } | 
 |  |  | 
 | void | void | 
| Line 185  ia32_step(void) | Line 172  ia32_step(void) | 
 |  |  | 
 | do { | do { | 
 | exec_1step(); | exec_1step(); | 
 | #if !defined(IA32_SUPPORT_DEBUG_REGISTER) |  | 
 | if (CPU_TRAP) { | if (CPU_TRAP) { | 
 | CPU_DR6 |= CPU_DR6_BS; | CPU_DR6 |= CPU_DR6_BS; | 
 | INTERRUPT(1, INTR_TYPE_EXCEPTION); | INTERRUPT(1, INTR_TYPE_EXCEPTION); | 
 | } | } | 
 | #endif |  | 
 | if (dmac.working) { | if (dmac.working) { | 
 | dmax86(); | dmax86(); | 
 | } | } | 
| Line 229  ia32_panic(const char *str, ...) | Line 214  ia32_panic(const char *str, ...) | 
 | va_end(ap); | va_end(ap); | 
 | strcat(buf, "\n"); | strcat(buf, "\n"); | 
 | strcat(buf, cpu_reg2str()); | strcat(buf, cpu_reg2str()); | 
 |  | VERBOSE(("%s", buf)); | 
 |  |  | 
 | msgbox("ia32_panic", buf); | msgbox("ia32_panic", buf); | 
 |  |  |