| version 1.7, 2004/01/23 14:33:26 | version 1.10, 2004/02/04 13:24:35 | 
| Line 33 | Line 33 | 
 |  |  | 
 | #include "dmap.h" | #include "dmap.h" | 
 | #include "bios.h" | #include "bios.h" | 
 |  | #if defined(IA32_REBOOT_ON_PANIC) | 
 |  | #include "pccore.h" | 
 |  | #endif | 
 |  |  | 
 |  |  | 
| void | static void ia32_initreg(void) { | 
| ia32reset(void) |  | 
| { |  | 
 | int i; | int i; | 
 |  |  | 
 | memset(&i386core.s, 0, sizeof(i386core.s)); |  | 
 | CPU_STATSAVE.cpu_inst_default.seg_base = (DWORD)-1; | CPU_STATSAVE.cpu_inst_default.seg_base = (DWORD)-1; | 
 |  |  | 
 | CPU_EDX = (CPU_FAMILY << 8) | (CPU_MODEL << 4) | CPU_STEPPING; | CPU_EDX = (CPU_FAMILY << 8) | (CPU_MODEL << 4) | CPU_STEPPING; | 
| Line 73  ia32reset(void) | Line 74  ia32reset(void) | 
 | } | } | 
 |  |  | 
 | void | void | 
 |  | ia32reset(void) | 
 |  | { | 
 |  |  | 
 |  | memset(&i386core.s, 0, sizeof(i386core.s)); | 
 |  | ia32_initreg(); | 
 |  | } | 
 |  |  | 
 |  | void | 
 | ia32shut(void) | ia32shut(void) | 
 | { | { | 
| SINT32  remainclock;                    /* 結局ハマるのか漏れ… */ |  | 
| SINT32  baseclock; | memset(&i386core.s, 0, offsetof(I386STAT, cpu_type)); | 
| UINT32  clock; | ia32_initreg(); | 
|  |  | 
| remainclock = CPU_REMCLOCK; |  | 
| baseclock = CPU_BASECLOCK; |  | 
| clock = CPU_CLOCK; |  | 
|  |  | 
| ia32reset(); |  | 
|  |  | 
| CPU_REMCLOCK = remainclock; |  | 
| CPU_BASECLOCK = baseclock; |  | 
| CPU_CLOCK = clock; |  | 
 | } | } | 
 |  |  | 
 | void | void | 
| Line 104  ia32(void) | Line 103  ia32(void) | 
 | VERBOSE(("ia32: return from exception")); | VERBOSE(("ia32: return from exception")); | 
 | break; | break; | 
 |  |  | 
 |  | case 2: | 
 |  | VERBOSE(("ia32: return from panic")); | 
 |  | return; | 
 |  |  | 
 | default: | default: | 
 | VERBOSE(("ia32: return from unknown cause")); | VERBOSE(("ia32: return from unknown cause")); | 
 | break; | break; | 
| Line 128  ia32withtrap(void) | Line 131  ia32withtrap(void) | 
 | VERBOSE(("ia32withtrap: return from exception")); | VERBOSE(("ia32withtrap: return from exception")); | 
 | break; | break; | 
 |  |  | 
 |  | case 2: | 
 |  | VERBOSE(("ia32withtrap: return from panic")); | 
 |  | return; | 
 |  |  | 
 | default: | default: | 
 | VERBOSE(("ia32withtrap: return from unknown cause")); | VERBOSE(("ia32withtrap: return from unknown cause")); | 
 | break; | break; | 
| Line 155  ia32withdma(void) | Line 162  ia32withdma(void) | 
 | VERBOSE(("ia32withdma: return from exception")); | VERBOSE(("ia32withdma: return from exception")); | 
 | break; | break; | 
 |  |  | 
 |  | case 2: | 
 |  | VERBOSE(("ia32withdma: return from panic")); | 
 |  | return; | 
 |  |  | 
 | default: | default: | 
 | VERBOSE(("ia32withdma: return from unknown cause")); | VERBOSE(("ia32withdma: return from unknown cause")); | 
 | break; | break; | 
| Line 180  ia32_step(void) | Line 191  ia32_step(void) | 
 | VERBOSE(("ia32_step: return from exception")); | VERBOSE(("ia32_step: return from exception")); | 
 | break; | break; | 
 |  |  | 
 |  | case 2: | 
 |  | VERBOSE(("ia32_step: return from panic")); | 
 |  | return; | 
 |  |  | 
 | default: | default: | 
 | VERBOSE(("ia32_step: return from unknown cause")); | VERBOSE(("ia32_step: return from unknown cause")); | 
 | break; | break; | 
| Line 220  ia32_panic(const char *str, ...) | Line 235  ia32_panic(const char *str, ...) | 
 |  |  | 
 | msgbox("ia32_panic", buf); | msgbox("ia32_panic", buf); | 
 |  |  | 
 |  | #if defined(IA32_REBOOT_ON_PANIC) | 
 |  | VERBOSE(("ia32_panic: reboot")); | 
 |  | pccore_cfgupdate(); | 
 |  | pccore_reset(); | 
 |  | siglongjmp(exec_1step_jmpbuf, 2); | 
 |  | #else | 
 | __ASSERT(0); | __ASSERT(0); | 
 | exit(1); | exit(1); | 
 |  | #endif | 
 | } | } | 
 |  |  | 
 | void | void | 
| Line 259  ia32_bioscall(void) | Line 281  ia32_bioscall(void) | 
 | { | { | 
 | DWORD adrs; | DWORD adrs; | 
 |  |  | 
| if (!CPU_STAT_PM && !CPU_INST_OP32 && !CPU_INST_AS32) { | if (!CPU_STAT_PM || CPU_STAT_VM86) { | 
| adrs = ((CPU_IP-1) & 0xffff) + CPU_STAT_SREGBASE(CPU_CS_INDEX); | adrs = (CPU_EIP - 1) + CPU_STAT_SREGBASE(CPU_CS_INDEX); | 
 | if ((adrs >= 0xf8000) && (adrs < 0x100000)) { | if ((adrs >= 0xf8000) && (adrs < 0x100000)) { | 
 | biosfunc(adrs); | biosfunc(adrs); | 
| CPU_SET_SEGREG(CPU_ES_INDEX, CPU_ES); | if (!CPU_STAT_PM || CPU_STAT_VM86) { | 
| CPU_SET_SEGREG(CPU_CS_INDEX, CPU_CS); | CPU_SET_SEGREG(CPU_ES_INDEX, CPU_ES); | 
| CPU_SET_SEGREG(CPU_SS_INDEX, CPU_SS); | CPU_SET_SEGREG(CPU_CS_INDEX, CPU_CS); | 
| CPU_SET_SEGREG(CPU_DS_INDEX, CPU_DS); | CPU_SET_SEGREG(CPU_SS_INDEX, CPU_SS); | 
|  | CPU_SET_SEGREG(CPU_DS_INDEX, CPU_DS); | 
|  | } | 
 | } | } | 
 | } | } | 
 | } | } |