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| version 1.5, 2004/01/07 06:53:48 | version 1.8, 2004/01/24 18:20:06 |
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| Line 30 | Line 30 |
| #include "compiler.h" | #include "compiler.h" |
| #include "cpu.h" | #include "cpu.h" |
| #include "ia32.mcr" | #include "ia32.mcr" |
| #include "dmap.h" | #include "dmap.h" |
| #include "bios.h" | #include "bios.h" |
| void | static void ia32_initreg(void) { |
| ia32reset(void) | |
| { | |
| int i; | int i; |
| memset(&i386core.s, 0, sizeof(i386core.s)); // yui | |
| CPU_STATSAVE.cpu_inst_default.seg_base = (DWORD)-1; | CPU_STATSAVE.cpu_inst_default.seg_base = (DWORD)-1; |
| CPU_EDX = (CPU_FAMILY << 8) | (CPU_MODEL << 4) | CPU_STEPPING; | CPU_EDX = (CPU_FAMILY << 8) | (CPU_MODEL << 4) | CPU_STEPPING; |
| CPU_EFLAG = 2; | CPU_EFLAG = 2; |
| CPU_CR0 = CPU_CR0_CD | CPU_CR0_NW | CPU_CR0_ET; | CPU_CR0 = CPU_CR0_CD | CPU_CR0_NW | CPU_CR0_ET; |
| #ifndef USE_FPU | |
| CPU_CR0 |= CPU_CR0_EM | CPU_CR0_NE; | |
| CPU_CR0 &= ~CPU_CR0_MP; | |
| #endif | |
| CPU_MXCSR = 0x1f80; | CPU_MXCSR = 0x1f80; |
| CPU_GDTR_LIMIT = 0xffff; | CPU_GDTR_LIMIT = 0xffff; |
| CPU_IDTR_LIMIT = 0xffff; | CPU_IDTR_LIMIT = 0xffff; |
| #if CPU_FAMILY == 4 | |
| CPU_STATSAVE.cpu_regs.dr[6] = 0xffff1ff0; | |
| #elif (CPU_FAMILY == 5) || (CPU_FAMILY == 6) | |
| CPU_STATSAVE.cpu_regs.dr[6] = 0xffff0ff0; | |
| CPU_STATSAVE.cpu_regs.dr[7] = 0x00000400; | |
| #endif | |
| for (i = 0; i < CPU_SEGREG_NUM; ++i) { | for (i = 0; i < CPU_SEGREG_NUM; ++i) { |
| CPU_STAT_SREG_INIT(i); | CPU_STAT_SREG_INIT(i); |
| } | } |
| CPU_LDTR_LIMIT = 0xffff; | CPU_LDTR_LIMIT = 0xffff; |
| CPU_TR_LIMIT = 0xffff; | CPU_TR_LIMIT = 0xffff; |
| // CPU_SET_SEGREG(CPU_ES_INDEX, 0x0000); | |
| CPU_SET_SEGREG(CPU_CS_INDEX, 0xf000); | CPU_SET_SEGREG(CPU_CS_INDEX, 0xf000); |
| // CPU_SET_SEGREG(CPU_SS_INDEX, 0x0000); | |
| // CPU_SET_SEGREG(CPU_DS_INDEX, 0x0000); | |
| CPU_EIP = 0xfff0; | CPU_EIP = 0xfff0; |
| CPU_ADRSMASK = 0xfffff; | CPU_ADRSMASK = 0x000fffff; |
| } | |
| void | |
| ia32reset(void) | |
| { | |
| ZeroMemory(&i386core.s, sizeof(i386core.s)); | |
| ia32_initreg(); | |
| } | } |
| void | void |
| ia32shut(void) | ia32shut(void) |
| { | { |
| SINT32 remainclock; // 結局ハマるのか漏れ… | ZeroMemory(&i386core.s, offsetof(I386STAT, cpu_type)); |
| SINT32 baseclock; | ia32_initreg(); |
| UINT32 clock; | |
| remainclock = CPU_REMCLOCK; | |
| baseclock = CPU_BASECLOCK; | |
| clock = CPU_CLOCK; | |
| ia32reset(); | |
| CPU_REMCLOCK = remainclock; | |
| CPU_BASECLOCK = baseclock; | |
| CPU_CLOCK = clock; | |
| } | } |
| void | void |
| Line 86 ia32(void) | Line 89 ia32(void) |
| { | { |
| int rv; | int rv; |
| #if defined(WIN32) | |
| rv = setjmp(exec_1step_jmpbuf); | |
| #else | |
| rv = sigsetjmp(exec_1step_jmpbuf, 1); | rv = sigsetjmp(exec_1step_jmpbuf, 1); |
| #endif | |
| switch (rv) { | switch (rv) { |
| case 0: | case 0: |
| break; | break; |
| case 1: | |
| VERBOSE(("ia32: return from exception")); | |
| break; | |
| default: | default: |
| CPU_EIP = CPU_PREV_EIP; | VERBOSE(("ia32: return from unknown cause")); |
| break; | break; |
| } | } |
| Line 110 ia32withtrap(void) | Line 113 ia32withtrap(void) |
| { | { |
| int rv; | int rv; |
| #if defined(WIN32) | |
| rv = setjmp(exec_1step_jmpbuf); | |
| #else | |
| rv = sigsetjmp(exec_1step_jmpbuf, 1); | rv = sigsetjmp(exec_1step_jmpbuf, 1); |
| #endif | |
| switch (rv) { | switch (rv) { |
| case 0: | case 0: |
| break; | break; |
| case 1: | |
| VERBOSE(("ia32withtrap: return from exception")); | |
| break; | |
| default: | default: |
| CPU_EIP = CPU_PREV_EIP; | VERBOSE(("ia32withtrap: return from unknown cause")); |
| break; | break; |
| } | } |
| do { | do { |
| exec_1step(); | exec_1step(); |
| if (CPU_TRAP) { | if (CPU_TRAP) { |
| Line 138 ia32withdma(void) | Line 140 ia32withdma(void) |
| { | { |
| int rv; | int rv; |
| #if defined(WIN32) | |
| rv = setjmp(exec_1step_jmpbuf); | |
| #else | |
| rv = sigsetjmp(exec_1step_jmpbuf, 1); | rv = sigsetjmp(exec_1step_jmpbuf, 1); |
| #endif | |
| switch (rv) { | switch (rv) { |
| case 0: | case 0: |
| break; | break; |
| case 1: | |
| VERBOSE(("ia32withdma: return from exception")); | |
| break; | |
| default: | default: |
| CPU_EIP = CPU_PREV_EIP; | VERBOSE(("ia32withdma: return from unknown cause")); |
| break; | break; |
| } | } |
| do { | do { |
| exec_1step(); | exec_1step(); |
| dmap_i286(); | dmap_i286(); |
| Line 164 ia32_step(void) | Line 165 ia32_step(void) |
| { | { |
| int rv; | int rv; |
| #if defined(WIN32) | |
| rv = setjmp(exec_1step_jmpbuf); | |
| #else | |
| rv = sigsetjmp(exec_1step_jmpbuf, 1); | rv = sigsetjmp(exec_1step_jmpbuf, 1); |
| #endif | |
| switch (rv) { | switch (rv) { |
| case 0: | case 0: |
| break; | break; |
| case 1: | |
| VERBOSE(("ia32_step: return from exception")); | |
| break; | |
| default: | default: |
| CPU_EIP = CPU_PREV_EIP; | VERBOSE(("ia32_step: return from unknown cause")); |
| break; | break; |
| } | } |
| do { | do { |
| exec_1step(); | exec_1step(); |
| if (CPU_TRAP) { | if (CPU_TRAP) { |
| Line 195 ia32_interrupt(BYTE vect) | Line 195 ia32_interrupt(BYTE vect) |
| INTERRUPT(vect, 0, 0, 0); | INTERRUPT(vect, 0, 0, 0); |
| } | } |
| /* | /* |
| * error function | * error function |
| */ | */ |
| void | void |
| ia32_panic(const char *str, ...) | ia32_panic(const char *str, ...) |
| { | { |
| char buf[1024]; | extern char *cpu_reg2str(void); |
| char buf[2048]; | |
| va_list ap; | va_list ap; |
| va_start(ap, str); | va_start(ap, str); |
| vsnprintf(buf, sizeof(buf), str, ap); | vsnprintf(buf, sizeof(buf), str, ap); |
| va_end(ap); | va_end(ap); |
| strcat(buf, "\n"); | strcat(buf, "\n"); |
| strcat(buf, cpu_reg2str()); | |
| #if defined(_WIN32) | msgbox("ia32_panic", buf); |
| MessageBox(NULL, buf, "ia32_panic", MB_OK); | |
| #endif | |
| fprintf(stderr, buf); | |
| __ASSERT(0); | __ASSERT(0); |
| exit(1); | exit(1); |
| } | } |
| Line 227 ia32_warning(const char *str, ...) | Line 228 ia32_warning(const char *str, ...) |
| va_end(ap); | va_end(ap); |
| strcat(buf, "\n"); | strcat(buf, "\n"); |
| fprintf(stderr, buf); | msgbox("ia32_warning", buf); |
| } | } |
| void | void |
| Line 238 ia32_printf(const char *str, ...) | Line 239 ia32_printf(const char *str, ...) |
| va_start(ap, str); | va_start(ap, str); |
| vsnprintf(buf, sizeof(buf), str, ap); | vsnprintf(buf, sizeof(buf), str, ap); |
| va_end(ap); | va_end(ap); |
| strcat(buf, "\n"); | |
| fprintf(stderr, buf); | msgbox("ia32_printf", buf); |
| } | } |
| /* | /* |
| * bios call interface | * bios call interface |
| */ | */ |
| void | void |
| ia32_bioscall(void) | ia32_bioscall(void) |
| { | { |
| DWORD adrs; | |
| /* XXX */ | |
| if (!CPU_STAT_PM && !CPU_INST_OP32 && !CPU_INST_AS32) { | if (!CPU_STAT_PM && !CPU_INST_OP32 && !CPU_INST_AS32) { |
| DWORD adrs; | |
| WORD sreg; | |
| adrs = ((CPU_IP-1) & 0xffff) + CPU_STAT_SREGBASE(CPU_CS_INDEX); | adrs = ((CPU_IP-1) & 0xffff) + CPU_STAT_SREGBASE(CPU_CS_INDEX); |
| if ((adrs >= 0xf8000) && (adrs < 0x100000)) { | if ((adrs >= 0xf8000) && (adrs < 0x100000)) { |
| biosfunc(adrs); | biosfunc(adrs); |
| sreg = CPU_ES; | CPU_SET_SEGREG(CPU_ES_INDEX, CPU_ES); |
| CPU_SET_SEGREG(CPU_ES_INDEX, sreg); | CPU_SET_SEGREG(CPU_CS_INDEX, CPU_CS); |
| sreg = CPU_CS; | CPU_SET_SEGREG(CPU_SS_INDEX, CPU_SS); |
| CPU_SET_SEGREG(CPU_CS_INDEX, sreg); | CPU_SET_SEGREG(CPU_DS_INDEX, CPU_DS); |
| sreg = CPU_SS; | |
| CPU_SET_SEGREG(CPU_SS_INDEX, sreg); | |
| sreg = CPU_DS; | |
| CPU_SET_SEGREG(CPU_DS_INDEX, sreg); | |
| } | } |
| } | } |
| } | } |