--- np2/i386c/ia32/interface.c 2004/02/18 20:11:37 1.12 +++ np2/i386c/ia32/interface.c 2008/03/22 04:03:07 1.27 @@ -1,4 +1,4 @@ -/* $Id: interface.c,v 1.12 2004/02/18 20:11:37 yui Exp $ */ +/* $Id: interface.c,v 1.27 2008/03/22 04:03:07 monaka Exp $ */ /* * Copyright (c) 2002-2003 NONAKA Kimihiro @@ -12,8 +12,6 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES @@ -30,8 +28,13 @@ #include "compiler.h" #include "cpu.h" #include "ia32.mcr" +#if defined(USE_FPU) +#include "instructions/fpu/fp.h" +#endif -#include "dmap.h" +#include "pccore.h" +#include "iocore.h" +#include "dmax86.h" #include "bios.h" #if defined(IA32_REBOOT_ON_PANIC) #include "pccore.h" @@ -43,35 +46,42 @@ ia32_initreg(void) { int i; - CPU_STATSAVE.cpu_inst_default.seg_base = (DWORD)-1; + CPU_STATSAVE.cpu_inst_default.seg_base = (UINT32)-1; CPU_EDX = (CPU_FAMILY << 8) | (CPU_MODEL << 4) | CPU_STEPPING; CPU_EFLAG = 2; CPU_CR0 = CPU_CR0_CD | CPU_CR0_NW | CPU_CR0_ET; -#ifndef USE_FPU +#if defined(USE_FPU) CPU_CR0 |= CPU_CR0_EM | CPU_CR0_NE; CPU_CR0 &= ~CPU_CR0_MP; +#else + CPU_CR0 |= CPU_CR0_ET; #endif CPU_MXCSR = 0x1f80; + + CPU_GDTR_BASE = 0x0; CPU_GDTR_LIMIT = 0xffff; + CPU_IDTR_BASE = 0x0; CPU_IDTR_LIMIT = 0xffff; + CPU_LDTR_BASE = 0x0; + CPU_LDTR_LIMIT = 0xffff; + CPU_TR_BASE = 0x0; + CPU_TR_LIMIT = 0xffff; -#if CPU_FAMILY == 4 CPU_STATSAVE.cpu_regs.dr[6] = 0xffff1ff0; -#elif (CPU_FAMILY == 5) || (CPU_FAMILY == 6) - CPU_STATSAVE.cpu_regs.dr[6] = 0xffff0ff0; - CPU_STATSAVE.cpu_regs.dr[7] = 0x00000400; -#endif for (i = 0; i < CPU_SEGREG_NUM; ++i) { - CPU_STAT_SREG_INIT(i); + segdesc_init(i, 0, &CPU_STAT_SREG(i)); } - CPU_LDTR_LIMIT = 0xffff; - CPU_TR_LIMIT = 0xffff; - - CPU_SET_SEGREG(CPU_CS_INDEX, 0xf000); + LOAD_SEGREG(CPU_CS_INDEX, 0xf000); + CPU_STAT_CS_BASE = 0xffff0000; CPU_EIP = 0xfff0; CPU_ADRSMASK = 0x000fffff; + + tlb_init(); +#if defined(USE_FPU) + fpu_init(); +#endif } void @@ -91,35 +101,14 @@ ia32shut(void) } void -ia32(void) +ia32a20enable(BOOL enable) { - int rv; - - rv = sigsetjmp(exec_1step_jmpbuf, 1); - switch (rv) { - case 0: - break; - - case 1: - VERBOSE(("ia32: return from exception")); - break; - - case 2: - VERBOSE(("ia32: return from panic")); - return; - default: - VERBOSE(("ia32: return from unknown cause")); - break; - } - - do { - exec_1step(); - } while (CPU_REMCLOCK > 0); + CPU_ADRSMASK = (enable)?0xffffffff:0x00ffffff; } void -ia32withtrap(void) +ia32(void) { int rv; @@ -129,53 +118,46 @@ ia32withtrap(void) break; case 1: - VERBOSE(("ia32withtrap: return from exception")); + VERBOSE(("ia32: return from exception")); break; case 2: - VERBOSE(("ia32withtrap: return from panic")); + VERBOSE(("ia32: return from panic")); return; default: - VERBOSE(("ia32withtrap: return from unknown cause")); + VERBOSE(("ia32: return from unknown cause")); break; } +#if defined(IA32_SUPPORT_DEBUG_REGISTER) do { exec_1step(); - if (CPU_TRAP) { - ia32_interrupt(1); + if (dmac.working) { + dmax86(); } } while (CPU_REMCLOCK > 0); -} - -void -ia32withdma(void) -{ - int rv; - - rv = sigsetjmp(exec_1step_jmpbuf, 1); - switch (rv) { - case 0: - break; - - case 1: - VERBOSE(("ia32withdma: return from exception")); - break; - - case 2: - VERBOSE(("ia32withdma: return from panic")); - return; - - default: - VERBOSE(("ia32withdma: return from unknown cause")); - break; +#else + if (CPU_TRAP) { + do { + exec_1step(); + if (CPU_TRAP) { + CPU_DR6 |= CPU_DR6_BS; + INTERRUPT(1, INTR_TYPE_EXCEPTION); + } + dmax86(); + } while (CPU_REMCLOCK > 0); + } else if (dmac.working) { + do { + exec_1step(); + dmax86(); + } while (CPU_REMCLOCK > 0); + } else { + do { + exec_1step(); + } while (CPU_REMCLOCK > 0); } - - do { - exec_1step(); - dmap_i286(); - } while (CPU_REMCLOCK > 0); +#endif } void @@ -203,18 +185,32 @@ ia32_step(void) do { exec_1step(); +#if !defined(IA32_SUPPORT_DEBUG_REGISTER) if (CPU_TRAP) { - ia32_interrupt(1); + CPU_DR6 |= CPU_DR6_BS; + INTERRUPT(1, INTR_TYPE_EXCEPTION); + } +#endif + if (dmac.working) { + dmax86(); } - dmap_i286(); } while (CPU_REMCLOCK > 0); } void CPUCALL -ia32_interrupt(REG8 vect) +ia32_interrupt(int vect, int soft) { - INTERRUPT(vect, 0, 0, 0); +// TRACEOUT(("int (%x, %x) PE=%d VM=%d", vect, soft, CPU_STAT_PM, CPU_STAT_VM86)); + if (!soft) { + INTERRUPT(vect, INTR_TYPE_EXTINTR); + } else { + if (CPU_STAT_PM && CPU_STAT_VM86 && CPU_STAT_IOPL < CPU_IOPL3) { + VERBOSE(("ia32_interrupt: VM86 && IOPL < 3 && INTn")); + EXCEPTION(GP_EXCEPTION, 0); + } + INTERRUPT(vect, INTR_TYPE_SOFTINTR); + } } @@ -238,7 +234,6 @@ ia32_panic(const char *str, ...) #if defined(IA32_REBOOT_ON_PANIC) VERBOSE(("ia32_panic: reboot")); - pccore_cfgupdate(); pccore_reset(); siglongjmp(exec_1step_jmpbuf, 2); #else @@ -280,18 +275,22 @@ ia32_printf(const char *str, ...) void ia32_bioscall(void) { - DWORD adrs; + UINT32 adrs; if (!CPU_STAT_PM || CPU_STAT_VM86) { - adrs = (CPU_EIP - 1) + CPU_STAT_SREGBASE(CPU_CS_INDEX); +#if 1 + adrs = CPU_PREV_EIP + (CPU_CS << 4); +#else + adrs = CPU_PREV_EIP + CPU_STAT_CS_BASE; +#endif if ((adrs >= 0xf8000) && (adrs < 0x100000)) { - biosfunc(adrs); - if (!CPU_STAT_PM || CPU_STAT_VM86) { - CPU_SET_SEGREG(CPU_ES_INDEX, CPU_ES); - CPU_SET_SEGREG(CPU_CS_INDEX, CPU_CS); - CPU_SET_SEGREG(CPU_SS_INDEX, CPU_SS); - CPU_SET_SEGREG(CPU_DS_INDEX, CPU_DS); + if (biosfunc(adrs)) { + /* Nothing to do */ } + LOAD_SEGREG(CPU_ES_INDEX, CPU_ES); + LOAD_SEGREG(CPU_CS_INDEX, CPU_CS); + LOAD_SEGREG(CPU_SS_INDEX, CPU_SS); + LOAD_SEGREG(CPU_DS_INDEX, CPU_DS); } } }