--- np2/i386c/ia32/interface.c	2004/03/06 18:07:37	1.15
+++ np2/i386c/ia32/interface.c	2005/03/12 12:32:54	1.24
@@ -1,4 +1,4 @@
-/*	$Id: interface.c,v 1.15 2004/03/06 18:07:37 monaka Exp $	*/
+/*	$Id: interface.c,v 1.24 2005/03/12 12:32:54 monaka Exp $	*/
 
 /*
  * Copyright (c) 2002-2003 NONAKA Kimihiro
@@ -12,8 +12,6 @@
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
@@ -30,10 +28,13 @@
 #include "compiler.h"
 #include "cpu.h"
 #include "ia32.mcr"
+#if defined(USE_FPU)
+#include "instructions/fpu/fp.h"
+#endif
 
 #include "pccore.h"
 #include "iocore.h"
-#include "dmap.h"
+#include "dmax86.h"
 #include "bios.h"
 #if defined(IA32_REBOOT_ON_PANIC)
 #include "pccore.h"
@@ -50,9 +51,11 @@ ia32_initreg(void)
 	CPU_EDX = (CPU_FAMILY << 8) | (CPU_MODEL << 4) | CPU_STEPPING;
 	CPU_EFLAG = 2;
 	CPU_CR0 = CPU_CR0_CD | CPU_CR0_NW | CPU_CR0_ET;
-#ifndef USE_FPU
+#if defined(USE_FPU)
 	CPU_CR0 |= CPU_CR0_EM | CPU_CR0_NE;
 	CPU_CR0 &= ~CPU_CR0_MP;
+#else
+	CPU_CR0 |= CPU_CR0_ET;
 #endif
 	CPU_MXCSR = 0x1f80;
 	CPU_GDTR_LIMIT = 0xffff;
@@ -60,7 +63,7 @@ ia32_initreg(void)
 
 #if CPU_FAMILY == 4
 	CPU_STATSAVE.cpu_regs.dr[6] = 0xffff1ff0;
-#elif (CPU_FAMILY == 5) || (CPU_FAMILY == 6)
+#elif CPU_FAMILY >= 5
 	CPU_STATSAVE.cpu_regs.dr[6] = 0xffff0ff0;
 	CPU_STATSAVE.cpu_regs.dr[7] = 0x00000400;
 #endif
@@ -76,6 +79,9 @@ ia32_initreg(void)
 	CPU_ADRSMASK = 0x000fffff;
 
 	tlb_init();
+#if defined(USE_FPU)
+	fpu_init();
+#endif
 }
 
 void
@@ -95,6 +101,16 @@ ia32shut(void)
 }
 
 void
+ia32a20enable(BOOL enable)
+{
+#if (CPU_FAMILY == 3)
+	CPU_ADRSMASK = (enable)?0x00ffffff:0x00ffffff;
+#else
+	CPU_ADRSMASK = (enable)?0xffffffff:0x00ffffff;
+#endif
+}
+
+void
 ia32(void)
 {
 	int rv;
@@ -117,24 +133,34 @@ ia32(void)
 		break;
 	}
 
+#if defined(IA32_SUPPORT_DEBUG_REGISTER)
+	do {
+		exec_1step();
+		if (dmac.working) {
+			dmax86();
+		}
+	} while (CPU_REMCLOCK > 0);
+#else
 	if (CPU_TRAP) {
 		do {
 			exec_1step();
 			if (CPU_TRAP) {
-				ia32_interrupt(1);
+				CPU_DR6 |= CPU_DR6_BS;
+				INTERRUPT(1, TRUE, FALSE, 0);
 			}
-			dmap_i286();
+			dmax86();
 		} while (CPU_REMCLOCK > 0);
 	} else if (dmac.working) {
 		do {
 			exec_1step();
-			dmap_i286();
+			dmax86();
 		} while (CPU_REMCLOCK > 0);
 	} else {
 		do {
 			exec_1step();
 		} while (CPU_REMCLOCK > 0);
 	}
+#endif
 }
 
 void
@@ -162,18 +188,32 @@ ia32_step(void)
 
 	do {
 		exec_1step();
+#if !defined(IA32_SUPPORT_DEBUG_REGISTER)
 		if (CPU_TRAP) {
-			ia32_interrupt(1);
+			CPU_DR6 |= CPU_DR6_BS;
+			INTERRUPT(1, TRUE, FALSE, 0);
+		}
+#endif
+		if (dmac.working) {
+			dmax86();
 		}
-		dmap_i286();
 	} while (CPU_REMCLOCK > 0);
 }
 
 void CPUCALL
-ia32_interrupt(int vect)
+ia32_interrupt(int vect, int soft)
 {
 
-	INTERRUPT(vect, 0, 0, 0);
+//	TRACEOUT(("int (%x, %x) PE=%d VM=%d",  vect, soft, CPU_STAT_PM, CPU_STAT_VM86));
+	if (!soft) {
+		INTERRUPT(vect, FALSE, FALSE, 0);
+	}
+	else {
+		if (CPU_STAT_VM86 && (CPU_STAT_IOPL < CPU_IOPL3) && (soft == -1)) {
+			TRACEOUT(("BIOS interrupt: VM86 && IOPL < 3 && INTn"));
+		}
+		INTERRUPT(vect, TRUE, FALSE, 0);
+	}
 }
 
 
@@ -197,7 +237,6 @@ ia32_panic(const char *str, ...)
 
 #if defined(IA32_REBOOT_ON_PANIC)
 	VERBOSE(("ia32_panic: reboot"));
-	pccore_cfgupdate();
 	pccore_reset();
 	siglongjmp(exec_1step_jmpbuf, 2);
 #else
@@ -242,9 +281,15 @@ ia32_bioscall(void)
 	UINT32 adrs;
 
 	if (!CPU_STAT_PM || CPU_STAT_VM86) {
+#if 1
+		adrs = (CPU_EIP - 1) + ((CPU_REGS_SREG(CPU_CS_INDEX)) << 4);
+#else
 		adrs = (CPU_EIP - 1) + CPU_STAT_CS_BASE;
+#endif
 		if ((adrs >= 0xf8000) && (adrs < 0x100000)) {
-			biosfunc(adrs);
+			if (biosfunc(adrs)) {
+				CPU_PREFETCH_CLEAR();
+			}
 			if (!CPU_STAT_PM || CPU_STAT_VM86) {
 				CPU_SET_SEGREG(CPU_ES_INDEX, CPU_ES);
 				CPU_SET_SEGREG(CPU_CS_INDEX, CPU_CS);