--- np2/i386c/ia32/interface.c	2003/12/08 02:09:17	1.2
+++ np2/i386c/ia32/interface.c	2004/03/09 18:52:12	1.18
@@ -1,4 +1,4 @@
-/*	$Id: interface.c,v 1.2 2003/12/08 02:09:17 yui Exp $	*/
+/*	$Id: interface.c,v 1.18 2004/03/09 18:52:12 yui Exp $	*/
 
 /*
  * Copyright (c) 2002-2003 NONAKA Kimihiro
@@ -30,98 +30,121 @@
 #include "compiler.h"
 #include "cpu.h"
 #include "ia32.mcr"
+
+#include "pccore.h"
+#include "iocore.h"
 #include "dmap.h"
 #include "bios.h"
-
-
-void
-ia32reset(void)
-{
-//	cpu_init();
-#ifdef USE_FPU		// ->ia32_init
-//	fpu_init();
+#if defined(IA32_REBOOT_ON_PANIC)
+#include "pccore.h"
 #endif
 
-	CPU_SET_SEGREG(CPU_CS_INDEX, 0x1fc0);
-	CPU_ADRSMASK = 0xfffff;
-}
 
 void
-ia32(void)
+ia32_initreg(void)
 {
-	int rv;
+	int i;
 
-#if defined(WIN32)
-	rv = setjmp(exec_1step_jmpbuf);
-#else
-	rv = sigsetjmp(exec_1step_jmpbuf, 1);
+	CPU_STATSAVE.cpu_inst_default.seg_base = (UINT32)-1;
+
+	CPU_EDX = (CPU_FAMILY << 8) | (CPU_MODEL << 4) | CPU_STEPPING;
+	CPU_EFLAG = 2;
+	CPU_CR0 = CPU_CR0_CD | CPU_CR0_NW | CPU_CR0_ET;
+#ifndef USE_FPU
+	CPU_CR0 |= CPU_CR0_EM | CPU_CR0_NE;
+	CPU_CR0 &= ~CPU_CR0_MP;
 #endif
-	switch (rv) {
-	case 0:
-		break;
-	
-	default:
-		CPU_EIP = CPU_PREV_EIP;
-		break;
+	CPU_MXCSR = 0x1f80;
+	CPU_GDTR_LIMIT = 0xffff;
+	CPU_IDTR_LIMIT = 0xffff;
+
+#if CPU_FAMILY == 4
+	CPU_STATSAVE.cpu_regs.dr[6] = 0xffff1ff0;
+#elif CPU_FAMILY >= 5
+	CPU_STATSAVE.cpu_regs.dr[6] = 0xffff0ff0;
+	CPU_STATSAVE.cpu_regs.dr[7] = 0x00000400;
+#endif
+
+	for (i = 0; i < CPU_SEGREG_NUM; ++i) {
+		CPU_STAT_SREG_INIT(i);
 	}
+	CPU_LDTR_LIMIT = 0xffff;
+	CPU_TR_LIMIT = 0xffff;
 
-	do {
-		exec_1step();
-	} while (CPU_REMCLOCK > 0);
+	CPU_SET_SEGREG(CPU_CS_INDEX, 0xf000);
+	CPU_EIP = 0xfff0;
+	CPU_ADRSMASK = 0x000fffff;
+
+	tlb_init();
 }
 
 void
-ia32withtrap(void)
+ia32reset(void)
 {
-	int rv;
 
-#if defined(WIN32)
-	rv = setjmp(exec_1step_jmpbuf);
-#else
-	rv = sigsetjmp(exec_1step_jmpbuf, 1);
-#endif
-	switch (rv) {
-	case 0:
-		break;
-	
-	default:
-		CPU_EIP = CPU_PREV_EIP;
-		break;
-	}
+	memset(&i386core.s, 0, sizeof(i386core.s));
+	ia32_initreg();
+}
 
+void
+ia32shut(void)
+{
 
-	do {
-		exec_1step();
-		if (CPU_TRAP) {
-			ia32_interrupt(1);
-		}
-	} while (CPU_REMCLOCK > 0);
+	memset(&i386core.s, 0, offsetof(I386STAT, cpu_type));
+	ia32_initreg();
 }
 
 void
-ia32withdma(void)
+ia32(void)
 {
 	int rv;
 
-#if defined(WIN32)
-	rv = setjmp(exec_1step_jmpbuf);
-#else
 	rv = sigsetjmp(exec_1step_jmpbuf, 1);
-#endif
 	switch (rv) {
 	case 0:
 		break;
-	
+
+	case 1:
+		VERBOSE(("ia32: return from exception"));
+		break;
+
+	case 2:
+		VERBOSE(("ia32: return from panic"));
+		return;
+
 	default:
-		CPU_EIP = CPU_PREV_EIP;
+		VERBOSE(("ia32: return from unknown cause"));
 		break;
 	}
 
-
+#if defined(IA32_SUPPORT_DEBUG_REGISTER)
 	do {
 		exec_1step();
-		dmap_i286();
+		if (dmac.working) {
+			dmap();
+		}
 	} while (CPU_REMCLOCK > 0);
+#else
+	if (CPU_TRAP) {
+		do {
+			exec_1step();
+			if (CPU_TRAP) {
+				CPU_DR6 |= CPU_DR6_BS;
+				INTERRUPT(1, TRUE, FALSE, 0);
+			}
+			dmap();
+		} while (CPU_REMCLOCK > 0);
+	} else if (dmac.working) {
+		do {
+			exec_1step();
+			dmap();
+		} while (CPU_REMCLOCK > 0);
+	} else {
+		do {
+			exec_1step();
+		} while (CPU_REMCLOCK > 0);
+	}
+#endif
 }
 
 void
@@ -129,53 +152,72 @@ ia32_step(void)
 {
 	int rv;
 
-#if defined(WIN32)
-	rv = setjmp(exec_1step_jmpbuf);
-#else
 	rv = sigsetjmp(exec_1step_jmpbuf, 1);
-#endif
 	switch (rv) {
 	case 0:
 		break;
-	
+
+	case 1:
+		VERBOSE(("ia32_step: return from exception"));
+		break;
+
+	case 2:
+		VERBOSE(("ia32_step: return from panic"));
+		return;
+
 	default:
-		CPU_EIP = CPU_PREV_EIP;
+		VERBOSE(("ia32_step: return from unknown cause"));
 		break;
 	}
 
-
 	do {
 		exec_1step();
+#if !defined(IA32_SUPPORT_DEBUG_REGISTER)
 		if (CPU_TRAP) {
-			ia32_interrupt(1);
+			CPU_DR6 |= CPU_DR6_BS;
+			INTERRUPT(1, TRUE, FALSE, 0);
+		}
+#endif
+		if (dmac.working) {
+			dmap();
 		}
-		dmap_i286();
 	} while (CPU_REMCLOCK > 0);
 }
 
 void CPUCALL
-ia32_interrupt(BYTE vect)
+ia32_interrupt(int vect)
 {
 
-	INTERRUPT(vect, 0, 0, 0);
+	INTERRUPT(vect, FALSE, FALSE, 0);
 }
 
+
 /*
  * error function
  */
 void
 ia32_panic(const char *str, ...)
 {
-	char buf[1024];
+	extern char *cpu_reg2str(void);
+	char buf[2048];
 	va_list ap;
+
 	va_start(ap, str);
 	vsnprintf(buf, sizeof(buf), str, ap);
 	va_end(ap);
 	strcat(buf, "\n");
+	strcat(buf, cpu_reg2str());
+
+	msgbox("ia32_panic", buf);
 
-	fprintf(stderr, buf);
+#if defined(IA32_REBOOT_ON_PANIC)
+	VERBOSE(("ia32_panic: reboot"));
+	pccore_reset();
+	siglongjmp(exec_1step_jmpbuf, 2);
+#else
 	__ASSERT(0);
 	exit(1);
+#endif
 }
 
 void
@@ -188,7 +230,7 @@ ia32_warning(const char *str, ...)
 	va_end(ap);
 	strcat(buf, "\n");
 
-	fprintf(stderr, buf);
+	msgbox("ia32_warning", buf);
 }
 
 void
@@ -199,33 +241,34 @@ ia32_printf(const char *str, ...)
 	va_start(ap, str);
 	vsnprintf(buf, sizeof(buf), str, ap);
 	va_end(ap);
+	strcat(buf, "\n");
 
-	fprintf(stderr, buf);
+	msgbox("ia32_printf", buf);
 }
 
+
 /*
  * bios call interface
  */
 void
 ia32_bioscall(void)
 {
+	UINT32 adrs;
 
-	/* XXX */
-	if (!CPU_STAT_PM && !CPU_INST_OP32 && !CPU_INST_AS32) {
-		DWORD adrs;
-		WORD sreg;
-
-		adrs = ((CPU_IP-1) & 0xffff) + CPU_STAT_SREGBASE(CPU_CS_INDEX);
+	if (!CPU_STAT_PM || CPU_STAT_VM86) {
+#if 1
+		adrs = (CPU_EIP - 1) + ((CPU_REGS_SREG(CPU_CS_INDEX)) << 4);
+#else
+		adrs = (CPU_EIP - 1) + CPU_STAT_CS_BASE;
+#endif
 		if ((adrs >= 0xf8000) && (adrs < 0x100000)) {
 			biosfunc(adrs);
-			sreg = CPU_ES;
-			CPU_SET_SEGREG(CPU_ES_INDEX, sreg);
-			sreg = CPU_CS;
-			CPU_SET_SEGREG(CPU_CS_INDEX, sreg);
-			sreg = CPU_SS;
-			CPU_SET_SEGREG(CPU_SS_INDEX, sreg);
-			sreg = CPU_DS;
-			CPU_SET_SEGREG(CPU_DS_INDEX, sreg);
+			if (!CPU_STAT_PM || CPU_STAT_VM86) {
+				CPU_SET_SEGREG(CPU_ES_INDEX, CPU_ES);
+				CPU_SET_SEGREG(CPU_CS_INDEX, CPU_CS);
+				CPU_SET_SEGREG(CPU_SS_INDEX, CPU_SS);
+				CPU_SET_SEGREG(CPU_DS_INDEX, CPU_DS);
+			}
 		}
 	}
 }