--- np2/i386c/ia32/interface.c	2004/05/23 15:01:45	1.21
+++ np2/i386c/ia32/interface.c	2011/01/15 17:17:23	1.28
@@ -1,5 +1,3 @@
-/*	$Id: interface.c,v 1.21 2004/05/23 15:01:45 yui Exp $	*/
-
 /*
  * Copyright (c) 2002-2003 NONAKA Kimihiro
  * All rights reserved.
@@ -12,8 +10,6 @@
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
@@ -30,10 +26,13 @@
 #include "compiler.h"
 #include "cpu.h"
 #include "ia32.mcr"
+#if defined(USE_FPU)
+#include "instructions/fpu/fp.h"
+#endif
 
 #include "pccore.h"
 #include "iocore.h"
-#include "dmap.h"
+#include "dmax86.h"
 #include "bios.h"
 #if defined(IA32_REBOOT_ON_PANIC)
 #include "pccore.h"
@@ -50,32 +49,37 @@ ia32_initreg(void)
 	CPU_EDX = (CPU_FAMILY << 8) | (CPU_MODEL << 4) | CPU_STEPPING;
 	CPU_EFLAG = 2;
 	CPU_CR0 = CPU_CR0_CD | CPU_CR0_NW | CPU_CR0_ET;
-#ifndef USE_FPU
+#if defined(USE_FPU)
 	CPU_CR0 |= CPU_CR0_EM | CPU_CR0_NE;
 	CPU_CR0 &= ~CPU_CR0_MP;
+#else
+	CPU_CR0 |= CPU_CR0_ET;
 #endif
 	CPU_MXCSR = 0x1f80;
+
+	CPU_GDTR_BASE = 0x0;
 	CPU_GDTR_LIMIT = 0xffff;
+	CPU_IDTR_BASE = 0x0;
 	CPU_IDTR_LIMIT = 0xffff;
+	CPU_LDTR_BASE = 0x0;
+	CPU_LDTR_LIMIT = 0xffff;
+	CPU_TR_BASE = 0x0;
+	CPU_TR_LIMIT = 0xffff;
 
-#if CPU_FAMILY == 4
 	CPU_STATSAVE.cpu_regs.dr[6] = 0xffff1ff0;
-#elif CPU_FAMILY >= 5
-	CPU_STATSAVE.cpu_regs.dr[6] = 0xffff0ff0;
-	CPU_STATSAVE.cpu_regs.dr[7] = 0x00000400;
-#endif
 
 	for (i = 0; i < CPU_SEGREG_NUM; ++i) {
-		CPU_STAT_SREG_INIT(i);
+		segdesc_init(i, 0, &CPU_STAT_SREG(i));
 	}
-	CPU_LDTR_LIMIT = 0xffff;
-	CPU_TR_LIMIT = 0xffff;
-
-	CPU_SET_SEGREG(CPU_CS_INDEX, 0xf000);
+	LOAD_SEGREG(CPU_CS_INDEX, 0xf000);
+	CPU_STAT_CS_BASE = 0xffff0000;
 	CPU_EIP = 0xfff0;
 	CPU_ADRSMASK = 0x000fffff;
 
 	tlb_init();
+#if defined(USE_FPU)
+	fpu_init();
+#endif
 }
 
 void
@@ -97,11 +101,8 @@ ia32shut(void)
 void
 ia32a20enable(BOOL enable)
 {
-#if (CPU_FAMILY == 3)
-	CPU_ADRSMASK = (enable)?0x00ffffff:0x00ffffff;
-#else
+
 	CPU_ADRSMASK = (enable)?0xffffffff:0x00ffffff;
-#endif
 }
 
 void
@@ -131,7 +132,7 @@ ia32(void)
 	do {
 		exec_1step();
 		if (dmac.working) {
-			dmap();
+			dmax86();
 		}
 	} while (CPU_REMCLOCK > 0);
 #else
@@ -140,14 +141,14 @@ ia32(void)
 			exec_1step();
 			if (CPU_TRAP) {
 				CPU_DR6 |= CPU_DR6_BS;
-				INTERRUPT(1, TRUE, FALSE, 0);
+				INTERRUPT(1, INTR_TYPE_EXCEPTION);
 			}
-			dmap();
+			dmax86();
 		} while (CPU_REMCLOCK > 0);
 	} else if (dmac.working) {
 		do {
 			exec_1step();
-			dmap();
+			dmax86();
 		} while (CPU_REMCLOCK > 0);
 	} else {
 		do {
@@ -185,11 +186,11 @@ ia32_step(void)
 #if !defined(IA32_SUPPORT_DEBUG_REGISTER)
 		if (CPU_TRAP) {
 			CPU_DR6 |= CPU_DR6_BS;
-			INTERRUPT(1, TRUE, FALSE, 0);
+			INTERRUPT(1, INTR_TYPE_EXCEPTION);
 		}
 #endif
 		if (dmac.working) {
-			dmap();
+			dmax86();
 		}
 	} while (CPU_REMCLOCK > 0);
 }
@@ -200,13 +201,13 @@ ia32_interrupt(int vect, int soft)
 
 //	TRACEOUT(("int (%x, %x) PE=%d VM=%d",  vect, soft, CPU_STAT_PM, CPU_STAT_VM86));
 	if (!soft) {
-		INTERRUPT(vect, FALSE, FALSE, 0);
-	}
-	else {
-		if (CPU_STAT_VM86 && (CPU_STAT_IOPL < CPU_IOPL3) && (soft == -1)) {
-			TRACEOUT(("BIOS interrupt: VM86 && IOPL < 3 && INTn"));
+		INTERRUPT(vect, INTR_TYPE_EXTINTR);
+	} else {
+		if (CPU_STAT_PM && CPU_STAT_VM86 && CPU_STAT_IOPL < CPU_IOPL3) {
+			VERBOSE(("ia32_interrupt: VM86 && IOPL < 3 && INTn"));
+			EXCEPTION(GP_EXCEPTION, 0);
 		}
-		INTERRUPT(vect, TRUE, FALSE, 0);
+		INTERRUPT(vect, INTR_TYPE_SOFTINTR);
 	}
 }
 
@@ -276,20 +277,18 @@ ia32_bioscall(void)
 
 	if (!CPU_STAT_PM || CPU_STAT_VM86) {
 #if 1
-		adrs = (CPU_EIP - 1) + ((CPU_REGS_SREG(CPU_CS_INDEX)) << 4);
+		adrs = CPU_PREV_EIP + (CPU_CS << 4);
 #else
-		adrs = (CPU_EIP - 1) + CPU_STAT_CS_BASE;
+		adrs = CPU_PREV_EIP + CPU_STAT_CS_BASE;
 #endif
 		if ((adrs >= 0xf8000) && (adrs < 0x100000)) {
 			if (biosfunc(adrs)) {
-				CPU_PREFETCH_CLEAR();
-			}
-			if (!CPU_STAT_PM || CPU_STAT_VM86) {
-				CPU_SET_SEGREG(CPU_ES_INDEX, CPU_ES);
-				CPU_SET_SEGREG(CPU_CS_INDEX, CPU_CS);
-				CPU_SET_SEGREG(CPU_SS_INDEX, CPU_SS);
-				CPU_SET_SEGREG(CPU_DS_INDEX, CPU_DS);
+				/* Nothing to do */
 			}
+			LOAD_SEGREG(CPU_ES_INDEX, CPU_ES);
+			LOAD_SEGREG(CPU_CS_INDEX, CPU_CS);
+			LOAD_SEGREG(CPU_SS_INDEX, CPU_SS);
+			LOAD_SEGREG(CPU_DS_INDEX, CPU_DS);
 		}
 	}
 }