--- np2/i386c/ia32/interface.c 2004/01/07 06:53:48 1.5 +++ np2/i386c/ia32/interface.c 2008/01/25 18:02:18 1.25 @@ -1,4 +1,4 @@ -/* $Id: interface.c,v 1.5 2004/01/07 06:53:48 yui Exp $ */ +/* $Id: interface.c,v 1.25 2008/01/25 18:02:18 monaka Exp $ */ /* * Copyright (c) 2002-2003 NONAKA Kimihiro @@ -12,8 +12,6 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES @@ -30,133 +28,139 @@ #include "compiler.h" #include "cpu.h" #include "ia32.mcr" -#include "dmap.h" +#if defined(USE_FPU) +#include "instructions/fpu/fp.h" +#endif + +#include "pccore.h" +#include "iocore.h" +#include "dmax86.h" #include "bios.h" +#if defined(IA32_REBOOT_ON_PANIC) +#include "pccore.h" +#endif void -ia32reset(void) +ia32_initreg(void) { int i; - memset(&i386core.s, 0, sizeof(i386core.s)); // yui - CPU_STATSAVE.cpu_inst_default.seg_base = (DWORD)-1; + CPU_STATSAVE.cpu_inst_default.seg_base = (UINT32)-1; CPU_EDX = (CPU_FAMILY << 8) | (CPU_MODEL << 4) | CPU_STEPPING; CPU_EFLAG = 2; CPU_CR0 = CPU_CR0_CD | CPU_CR0_NW | CPU_CR0_ET; +#if defined(USE_FPU) + CPU_CR0 |= CPU_CR0_EM | CPU_CR0_NE; + CPU_CR0 &= ~CPU_CR0_MP; +#else + CPU_CR0 |= CPU_CR0_ET; +#endif CPU_MXCSR = 0x1f80; CPU_GDTR_LIMIT = 0xffff; CPU_IDTR_LIMIT = 0xffff; +#if CPU_FAMILY == 4 + CPU_STATSAVE.cpu_regs.dr[6] = 0xffff1ff0; +#elif CPU_FAMILY >= 5 + CPU_STATSAVE.cpu_regs.dr[6] = 0xffff0ff0; + CPU_STATSAVE.cpu_regs.dr[7] = 0x00000400; +#endif + for (i = 0; i < CPU_SEGREG_NUM; ++i) { CPU_STAT_SREG_INIT(i); } CPU_LDTR_LIMIT = 0xffff; CPU_TR_LIMIT = 0xffff; -// CPU_SET_SEGREG(CPU_ES_INDEX, 0x0000); CPU_SET_SEGREG(CPU_CS_INDEX, 0xf000); -// CPU_SET_SEGREG(CPU_SS_INDEX, 0x0000); -// CPU_SET_SEGREG(CPU_DS_INDEX, 0x0000); CPU_EIP = 0xfff0; - CPU_ADRSMASK = 0xfffff; + CPU_ADRSMASK = 0x000fffff; + + tlb_init(); +#if defined(USE_FPU) + fpu_init(); +#endif } void -ia32shut(void) +ia32reset(void) { - SINT32 remainclock; // 結局ハマるのか漏れ… - SINT32 baseclock; - UINT32 clock; - - remainclock = CPU_REMCLOCK; - baseclock = CPU_BASECLOCK; - clock = CPU_CLOCK; - - ia32reset(); - - CPU_REMCLOCK = remainclock; - CPU_BASECLOCK = baseclock; - CPU_CLOCK = clock; + + memset(&i386core.s, 0, sizeof(i386core.s)); + ia32_initreg(); } void -ia32(void) +ia32shut(void) { - int rv; - -#if defined(WIN32) - rv = setjmp(exec_1step_jmpbuf); -#else - rv = sigsetjmp(exec_1step_jmpbuf, 1); -#endif - switch (rv) { - case 0: - break; - - default: - CPU_EIP = CPU_PREV_EIP; - break; - } - do { - exec_1step(); - } while (CPU_REMCLOCK > 0); + memset(&i386core.s, 0, offsetof(I386STAT, cpu_type)); + ia32_initreg(); } void -ia32withtrap(void) +ia32a20enable(BOOL enable) { - int rv; - -#if defined(WIN32) - rv = setjmp(exec_1step_jmpbuf); +#if (CPU_FAMILY == 3) + CPU_ADRSMASK = (enable)?0x00ffffff:0x00ffffff; #else - rv = sigsetjmp(exec_1step_jmpbuf, 1); + CPU_ADRSMASK = (enable)?0xffffffff:0x00ffffff; #endif - switch (rv) { - case 0: - break; - - default: - CPU_EIP = CPU_PREV_EIP; - break; - } - - - do { - exec_1step(); - if (CPU_TRAP) { - ia32_interrupt(1); - } - } while (CPU_REMCLOCK > 0); } void -ia32withdma(void) +ia32(void) { int rv; -#if defined(WIN32) - rv = setjmp(exec_1step_jmpbuf); -#else rv = sigsetjmp(exec_1step_jmpbuf, 1); -#endif switch (rv) { case 0: break; - + + case 1: + VERBOSE(("ia32: return from exception")); + break; + + case 2: + VERBOSE(("ia32: return from panic")); + return; + default: - CPU_EIP = CPU_PREV_EIP; + VERBOSE(("ia32: return from unknown cause")); break; } - +#if defined(IA32_SUPPORT_DEBUG_REGISTER) do { exec_1step(); - dmap_i286(); + if (dmac.working) { + dmax86(); + } } while (CPU_REMCLOCK > 0); +#else + if (CPU_TRAP) { + do { + exec_1step(); + if (CPU_TRAP) { + CPU_DR6 |= CPU_DR6_BS; + INTERRUPT(1, TRUE, FALSE, 0); + } + dmax86(); + } while (CPU_REMCLOCK > 0); + } else if (dmac.working) { + do { + exec_1step(); + dmax86(); + } while (CPU_REMCLOCK > 0); + } else { + do { + exec_1step(); + } while (CPU_REMCLOCK > 0); + } +#endif } void @@ -164,57 +168,81 @@ ia32_step(void) { int rv; -#if defined(WIN32) - rv = setjmp(exec_1step_jmpbuf); -#else rv = sigsetjmp(exec_1step_jmpbuf, 1); -#endif switch (rv) { case 0: break; - + + case 1: + VERBOSE(("ia32_step: return from exception")); + break; + + case 2: + VERBOSE(("ia32_step: return from panic")); + return; + default: - CPU_EIP = CPU_PREV_EIP; + VERBOSE(("ia32_step: return from unknown cause")); break; } - do { exec_1step(); +#if !defined(IA32_SUPPORT_DEBUG_REGISTER) if (CPU_TRAP) { - ia32_interrupt(1); + CPU_DR6 |= CPU_DR6_BS; + INTERRUPT(1, TRUE, FALSE, 0); + } +#endif + if (dmac.working) { + dmax86(); } - dmap_i286(); } while (CPU_REMCLOCK > 0); } void CPUCALL -ia32_interrupt(BYTE vect) +ia32_interrupt(int vect, int soft) { - INTERRUPT(vect, 0, 0, 0); +// TRACEOUT(("int (%x, %x) PE=%d VM=%d", vect, soft, CPU_STAT_PM, CPU_STAT_VM86)); + if (!soft) { + INTERRUPT(vect, FALSE, FALSE, 0); + } + else { + if (CPU_STAT_VM86 && (CPU_STAT_IOPL < CPU_IOPL3) && (soft == -1)) { + TRACEOUT(("BIOS interrupt: VM86 && IOPL < 3 && INTn")); + } + INTERRUPT(vect, TRUE, FALSE, 0); + } } + /* * error function */ void ia32_panic(const char *str, ...) { - char buf[1024]; + extern char *cpu_reg2str(void); + char buf[2048]; va_list ap; + va_start(ap, str); vsnprintf(buf, sizeof(buf), str, ap); va_end(ap); strcat(buf, "\n"); + strcat(buf, cpu_reg2str()); -#if defined(_WIN32) - MessageBox(NULL, buf, "ia32_panic", MB_OK); -#endif + msgbox("ia32_panic", buf); - fprintf(stderr, buf); +#if defined(IA32_REBOOT_ON_PANIC) + VERBOSE(("ia32_panic: reboot")); + pccore_reset(); + siglongjmp(exec_1step_jmpbuf, 2); +#else __ASSERT(0); exit(1); +#endif } void @@ -227,7 +255,7 @@ ia32_warning(const char *str, ...) va_end(ap); strcat(buf, "\n"); - fprintf(stderr, buf); + msgbox("ia32_warning", buf); } void @@ -238,33 +266,33 @@ ia32_printf(const char *str, ...) va_start(ap, str); vsnprintf(buf, sizeof(buf), str, ap); va_end(ap); + strcat(buf, "\n"); - fprintf(stderr, buf); + msgbox("ia32_printf", buf); } + /* * bios call interface */ void ia32_bioscall(void) { + UINT32 adrs; - /* XXX */ - if (!CPU_STAT_PM && !CPU_INST_OP32 && !CPU_INST_AS32) { - DWORD adrs; - WORD sreg; - - adrs = ((CPU_IP-1) & 0xffff) + CPU_STAT_SREGBASE(CPU_CS_INDEX); + if (!CPU_STAT_PM || CPU_STAT_VM86) { +#if 1 + adrs = (CPU_EIP - 1) + ((CPU_REGS_SREG(CPU_CS_INDEX)) << 4); +#else + adrs = (CPU_EIP - 1) + CPU_STAT_CS_BASE; +#endif if ((adrs >= 0xf8000) && (adrs < 0x100000)) { - biosfunc(adrs); - sreg = CPU_ES; - CPU_SET_SEGREG(CPU_ES_INDEX, sreg); - sreg = CPU_CS; - CPU_SET_SEGREG(CPU_CS_INDEX, sreg); - sreg = CPU_SS; - CPU_SET_SEGREG(CPU_SS_INDEX, sreg); - sreg = CPU_DS; - CPU_SET_SEGREG(CPU_DS_INDEX, sreg); + if (!CPU_STAT_PM || CPU_STAT_VM86) { + CPU_SET_SEGREG(CPU_ES_INDEX, CPU_ES); + CPU_SET_SEGREG(CPU_CS_INDEX, CPU_CS); + CPU_SET_SEGREG(CPU_SS_INDEX, CPU_SS); + CPU_SET_SEGREG(CPU_DS_INDEX, CPU_DS); + } } } }