--- np2/i386c/ia32/interface.c	2011/01/15 17:17:23	1.28
+++ np2/i386c/ia32/interface.c	2012/01/08 11:36:06	1.31
@@ -34,9 +34,6 @@
 #include "iocore.h"
 #include "dmax86.h"
 #include "bios.h"
-#if defined(IA32_REBOOT_ON_PANIC)
-#include "pccore.h"
-#endif
 
 
 void
@@ -50,10 +47,10 @@ ia32_initreg(void)
 	CPU_EFLAG = 2;
 	CPU_CR0 = CPU_CR0_CD | CPU_CR0_NW | CPU_CR0_ET;
 #if defined(USE_FPU)
-	CPU_CR0 |= CPU_CR0_EM | CPU_CR0_NE;
-	CPU_CR0 &= ~CPU_CR0_MP;
-#else
 	CPU_CR0 |= CPU_CR0_ET;
+#else
+	CPU_CR0 |= CPU_CR0_EM | CPU_CR0_NE;
+	CPU_CR0 &= ~(CPU_CR0_MP | CPU_CR0_ET);
 #endif
 	CPU_MXCSR = 0x1f80;
 
@@ -128,14 +125,6 @@ ia32(void)
 		break;
 	}
 
-#if defined(IA32_SUPPORT_DEBUG_REGISTER)
-	do {
-		exec_1step();
-		if (dmac.working) {
-			dmax86();
-		}
-	} while (CPU_REMCLOCK > 0);
-#else
 	if (CPU_TRAP) {
 		do {
 			exec_1step();
@@ -155,7 +144,6 @@ ia32(void)
 			exec_1step();
 		} while (CPU_REMCLOCK > 0);
 	}
-#endif
 }
 
 void
@@ -183,12 +171,10 @@ ia32_step(void)
 
 	do {
 		exec_1step();
-#if !defined(IA32_SUPPORT_DEBUG_REGISTER)
 		if (CPU_TRAP) {
 			CPU_DR6 |= CPU_DR6_BS;
 			INTERRUPT(1, INTR_TYPE_EXCEPTION);
 		}
-#endif
 		if (dmac.working) {
 			dmax86();
 		}