--- np2/i386c/ia32/interface.c	2003/12/08 02:09:17	1.2
+++ np2/i386c/ia32/interface.c	2004/01/07 06:53:48	1.5
@@ -1,4 +1,4 @@
-/*	$Id: interface.c,v 1.2 2003/12/08 02:09:17 yui Exp $	*/
+/*	$Id: interface.c,v 1.5 2004/01/07 06:53:48 yui Exp $	*/
 
 /*
  * Copyright (c) 2002-2003 NONAKA Kimihiro
@@ -37,16 +37,51 @@
 void
 ia32reset(void)
 {
-//	cpu_init();
-#ifdef USE_FPU		// ->ia32_init
-//	fpu_init();
-#endif
+	int i;
+
+	memset(&i386core.s, 0, sizeof(i386core.s));			// yui
+	CPU_STATSAVE.cpu_inst_default.seg_base = (DWORD)-1;
+
+	CPU_EDX = (CPU_FAMILY << 8) | (CPU_MODEL << 4) | CPU_STEPPING;
+	CPU_EFLAG = 2;
+	CPU_CR0 = CPU_CR0_CD | CPU_CR0_NW | CPU_CR0_ET;
+	CPU_MXCSR = 0x1f80;
+	CPU_GDTR_LIMIT = 0xffff;
+	CPU_IDTR_LIMIT = 0xffff;
 
-	CPU_SET_SEGREG(CPU_CS_INDEX, 0x1fc0);
+	for (i = 0; i < CPU_SEGREG_NUM; ++i) {
+		CPU_STAT_SREG_INIT(i);
+	}
+	CPU_LDTR_LIMIT = 0xffff;
+	CPU_TR_LIMIT = 0xffff;
+
+//	CPU_SET_SEGREG(CPU_ES_INDEX, 0x0000);
+	CPU_SET_SEGREG(CPU_CS_INDEX, 0xf000);
+//	CPU_SET_SEGREG(CPU_SS_INDEX, 0x0000);
+//	CPU_SET_SEGREG(CPU_DS_INDEX, 0x0000);
+	CPU_EIP = 0xfff0;
 	CPU_ADRSMASK = 0xfffff;
 }
 
 void
+ia32shut(void)
+{
+	SINT32	remainclock;					// 結局ハマるのか漏れ…
+	SINT32	baseclock;
+	UINT32	clock;
+
+	remainclock = CPU_REMCLOCK;
+	baseclock = CPU_BASECLOCK;
+	clock = CPU_CLOCK;
+
+	ia32reset();
+
+	CPU_REMCLOCK = remainclock;
+	CPU_BASECLOCK = baseclock;
+	CPU_CLOCK = clock;
+}
+
+void
 ia32(void)
 {
 	int rv;
@@ -173,6 +208,10 @@ ia32_panic(const char *str, ...)
 	va_end(ap);
 	strcat(buf, "\n");
 
+#if defined(_WIN32)
+	MessageBox(NULL, buf, "ia32_panic", MB_OK);
+#endif
+
 	fprintf(stderr, buf);
 	__ASSERT(0);
 	exit(1);