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| version 1.10, 2004/02/04 13:24:35 | version 1.11, 2004/02/05 16:43:44 |
|---|---|
| Line 212 cpu_linear_memory_read(DWORD laddr, DWOR | Line 212 cpu_linear_memory_read(DWORD laddr, DWOR |
| break; | break; |
| case 3: | case 3: |
| value |= (DWORD)cpu_memoryread(paddr) << shift; | value += (DWORD)cpu_memoryread(paddr) << shift; |
| shift += 8; | shift += 8; |
| paddr++; | paddr++; |
| /*FALLTHROUGH*/ | /*FALLTHROUGH*/ |
| case 2: | case 2: |
| value |= (DWORD)cpu_memoryread_w(paddr) << shift; | value += (DWORD)cpu_memoryread_w(paddr) << shift; |
| shift += 16; | shift += 16; |
| break; | break; |
| case 1: | case 1: |
| value |= (DWORD)cpu_memoryread(paddr) << shift; | value += (DWORD)cpu_memoryread(paddr) << shift; |
| shift += 8; | shift += 8; |
| break; | break; |
| Line 341 paging(DWORD laddr, int crw, int user_mo | Line 341 paging(DWORD laddr, int crw, int user_mo |
| return paddr; | return paddr; |
| #endif /* IA32_SUPPORT_TLB */ | #endif /* IA32_SUPPORT_TLB */ |
| pde_addr = CPU_STAT_PDE_BASE | ((laddr >> 20) & 0xffc); | pde_addr = CPU_STAT_PDE_BASE + ((laddr >> 20) & 0xffc); |
| pde = cpu_memoryread_d(pde_addr); | pde = cpu_memoryread_d(pde_addr); |
| if (!(pde & CPU_PDE_PRESENT)) { | if (!(pde & CPU_PDE_PRESENT)) { |
| VERBOSE(("paging: PDE is not present")); | VERBOSE(("paging: PTE page is not present")); |
| VERBOSE(("paging: CPU_CR3 = 0x%08x", CPU_CR3)); | VERBOSE(("paging: CPU_CR3 = 0x%08x", CPU_CR3)); |
| VERBOSE(("paging: laddr = 0x%08x, pde_addr = 0x%08x, pde = 0x%08x", laddr, pde_addr, pde)); | VERBOSE(("paging: laddr = 0x%08x, pde_addr = 0x%08x, pde = 0x%08x", laddr, pde_addr, pde)); |
| err = 0; | err = 0; |
| Line 367 paging(DWORD laddr, int crw, int user_mo | Line 367 paging(DWORD laddr, int crw, int user_mo |
| pte_addr = 0; /* compiler happy */ | pte_addr = 0; /* compiler happy */ |
| /* make physical address */ | /* make physical address */ |
| paddr = (pde & CPU_PDE_4M_BASEADDR_MASK) | (laddr & 0x003fffff); | paddr = (pde & CPU_PDE_4M_BASEADDR_MASK) + (laddr & 0x003fffff); |
| } else | } else |
| #endif /* CPU_FAMILY >= 5 */ | #endif /* CPU_FAMILY >= 5 */ |
| { | { |
| /* 4KB page size */ | /* 4KB page size */ |
| pte_addr = (pde & CPU_PDE_BASEADDR_MASK) | ((laddr >> 10) & 0xffc); | pte_addr = (pde & CPU_PDE_BASEADDR_MASK) + ((laddr >> 10) & 0xffc); |
| pte = cpu_memoryread_d(pte_addr); | pte = cpu_memoryread_d(pte_addr); |
| if (!(pte & CPU_PTE_PRESENT)) { | if (!(pte & CPU_PTE_PRESENT)) { |
| VERBOSE(("paging: PTE is not present")); | VERBOSE(("paging: page is not present")); |
| VERBOSE(("paging: laddr = 0x%08x, pde_addr = 0x%08x, pde = 0x%08x", laddr, pde_addr, pde)); | VERBOSE(("paging: laddr = 0x%08x, pde_addr = 0x%08x, pde = 0x%08x", laddr, pde_addr, pde)); |
| VERBOSE(("paging: pte_addr = 0x%08x, pte = 0x%08x", pte_addr, pte)); | VERBOSE(("paging: pte_addr = 0x%08x, pte = 0x%08x", pte_addr, pte)); |
| err = 0; | err = 0; |
| Line 387 paging(DWORD laddr, int crw, int user_mo | Line 387 paging(DWORD laddr, int crw, int user_mo |
| } | } |
| /* make physical address */ | /* make physical address */ |
| paddr = (pte & CPU_PTE_BASEADDR_MASK) | (laddr & 0x00000fff); | paddr = (pte & CPU_PTE_BASEADDR_MASK) + (laddr & 0x00000fff); |
| } | } |
| bit = crw & CPU_PAGE_WRITE; | bit = crw & CPU_PAGE_WRITE; |
| bit |= (pde & pte & (CPU_PTE_WRITABLE|CPU_PTE_USER_MODE)); | bit |= (pde & pte & (CPU_PTE_WRITABLE|CPU_PTE_USER_MODE)); |
| bit |= (user_mode << 3); | bit |= (user_mode << 3); |
| bit |= (CPU_CR0 & CPU_CR0_WP) >> 12; | bit |= CPU_STAT_WP; |
| #if !defined(USE_PAGE_ACCESS_TABLE) | #if !defined(USE_PAGE_ACCESS_TABLE) |
| if (!(page_access & (1 << bit))) | if (!(page_access & (1 << bit))) |