np2/i386c/ia32/paging.c - diff

Return to paging.c CVS log

Up to [RetroPC.NET] / np2 / i386c / ia32

Diff for /np2/i386c/ia32/paging.c between versions 1.1 and 1.12

version 1.1, 2003/12/08 00:55:31	version 1.12, 2004/02/20 16:09:04
Line 32	Line 32
#include "ia32.mcr"	#include "ia32.mcr"

/*	/*
* ページ・ディレクトリ・エントリ (4K バイトページ使用時)
*
* 31 12 11 9 8 7 6 5 4 3 2 1 0
* +----------------------------------------+------+-+--+-+-+---+---+---+---+-+
* \| ページ・テーブルのベース・アドレス \|使用可\|G\|PS\|0\|A\|PCD\|PWT\|U/S\|R/W\|P\|
* +----------------------------------------+------+-+--+-+-+---+---+---+---+-+
* \| \| \| \| \| \| \| \| \| \|
* 9-11: システム・プログラマが使用可能 --------+ \| \| \| \| \| \| \| \| \|
* 8: グローバル・ページ(無視される) ------------+ \| \| \| \| \| \| \| \|
* 7: ページ・サイズ (0 = 4k バイトページ) ---------+ \| \| \| \| \| \| \|
* 6: 予約 (0) ---------------------------------------+ \| \| \| \| \| \|
* 5: アクセス -----------------------------------------+ \| \| \| \| \|
* 4: キャッシュ無効 --------------------------------------+ \| \| \| \|
* 3: ライトスルー --------------------------------------------+ \| \| \|
* 2: ユーザ／スーパバイザ (0 = スーパバイザ) ---------------------+ \| \|
* 1: 読み取り／書き込み (0 = 読み取りのみ) ---------------------------+ \|
* 0: ページ存在 ---------------------------------------------------------+
*/
#define CPU_PDE_BASEADDR_MASK 0xfffff000
#define CPU_PDE_PAGE_SIZE (1 << 7)
#define CPU_PDE_ACCESS (1 << 5)
#define CPU_PDE_CACHE_DISABLE (1 << 4)
#define CPU_PDE_WRITE_THROUGH (1 << 3)
#define CPU_PDE_USER_MODE (1 << 2)
#define CPU_PDE_WRITABLE (1 << 1)
#define CPU_PDE_PRESENT (1 << 0)

/*
* ページ・ディレクトリ・エントリ (4M バイトページ使用時)
*
* 31 22 21 12 11 9 8 7 6 5 4 3 2 1 0
* +----------------------------+-----------+------+-+--+-+-+---+---+---+---+-+
* \|ページテーブルの物理アドレス\| 予約済み \|使用可\|G\|PS\|D\|A\|PCD\|PWT\|U/S\|R/W\|P\|
* +----------------------------+-----------+------+-+--+-+-+---+---+---+---+-+
* \| \| \| \| \| \| \| \| \| \|
* 9-11: システム・プログラマが使用可能 --------+ \| \| \| \| \| \| \| \| \|
* 8: グローバル・ページ ------------------------+ \| \| \| \| \| \| \| \|
* 7: ページ・サイズ (1 = 4M バイトページ) ---------+ \| \| \| \| \| \| \|
* 6: ダーティ ---------------------------------------+ \| \| \| \| \| \|
* 5: アクセス -----------------------------------------+ \| \| \| \| \|
* 4: キャッシュ無効 --------------------------------------+ \| \| \| \|
* 3: ライトスルー --------------------------------------------+ \| \| \|
* 2: ユーザ／スーパバイザ (0 = スーパバイザ) ---------------------+ \| \|
* 1: 読み取り／書き込み (0 = 読み取りのみ) ---------------------------+ \|
* 0: ページ存在 ---------------------------------------------------------+
*/
#define CPU_PDE_4M_BASEADDR_MASK 0xffc00000
#define CPU_PDE_4M_GLOBAL_PAGE (1 << 8)
#define CPU_PDE_4M_PAGE_SIZE (1 << 7)
#define CPU_PDE_4M_DIRTY (1 << 6)
#define CPU_PDE_4M_ACCESS (1 << 5)
#define CPU_PDE_4M_CACHE_DISABLE (1 << 4)
#define CPU_PDE_4M_WRITE_THROUGH (1 << 3)
#define CPU_PDE_4M_USER_MODE (1 << 2)
#define CPU_PDE_4M_WRITABLE (1 << 1)
#define CPU_PDE_4M_PRESENT (1 << 0)

/*
* ページ・テーブル・エントリ (4k バイト・ページ)
*
* 31 12 11 9 8 7 6 5 4 3 2 1 0
* +----------------------------------------+------+-+-+-+-+---+---+---+---+-+
* \| ページのベース・アドレス \|使用可\|G\|0\|D\|A\|PCD\|PWT\|U/S\|R/W\|P\|
* +----------------------------------------+------+-+-+-+-+---+---+---+---+-+
* \| \| \| \| \| \| \| \| \| \|
* 9-11: システム・プログラマが使用可能 -------+ \| \| \| \| \| \| \| \| \|
* 8: グローバル・ページ -----------------------+ \| \| \| \| \| \| \| \|
* 7: 予約 (0) -----------------------------------+ \| \| \| \| \| \| \|
* 6: ダーティ -------------------------------------+ \| \| \| \| \| \|
* 5: アクセス ---------------------------------------+ \| \| \| \| \|
* 4: キャッシュ無効 ------------------------------------+ \| \| \| \|
* 3: ライトスルー ------------------------------------------+ \| \| \|
* 2: ユーザ／スーパバイザ (0 = スーパバイザ) -------------------+ \| \|
* 1: 読み取り／書き込み (0 = 読み取りのみ) -------------------------+ \|
* 0: ページ存在 -------------------------------------------------------+
*/
#define CPU_PTE_BASEADDR_MASK 0xfffff000
#define CPU_PTE_GLOBAL_PAGE (1 << 8)
#define CPU_PTE_DIRTY (1 << 6)
#define CPU_PTE_ACCESS (1 << 5)
#define CPU_PTE_CACHE_DISABLE (1 << 4)
#define CPU_PTE_WRITE_THROUGH (1 << 3)
#define CPU_PTE_USER_MODE (1 << 2)
#define CPU_PTE_WRITABLE (1 << 1)
#define CPU_PTE_PRESENT (1 << 0)

/*
* ページフォルト例外	* ページフォルト例外
*	*
* 4-31: 予約済み	* 4-31: 予約済み
Line 199	Line 112
* +-----+-----------+-----+-----+---+	* +-----+-----------+-----+-----+---+
*/	*/
#if !defined(USE_PAGE_ACCESS_TABLE)	#if !defined(USE_PAGE_ACCESS_TABLE)
static const DWORD page_access = 0xd0cdd0ff;	#define page_access 0xd0ddd0ff
#else /* USE_PAGE_ACCESS_TABLE */	#else /* USE_PAGE_ACCESS_TABLE */
static const BYTE page_access_bit[32] = {	static const UINT8 page_access_bit[32] = {
1, /* CR0: n, CPL: s, PTE: s, PTE: r, ope: r */	1, /* CR0: n, CPL: s, PTE: s, PTE: r, ope: r */
1, /* CR0: n, CPL: s, PTE: s, PTE: r, ope: w */	1, /* CR0: n, CPL: s, PTE: s, PTE: r, ope: w */
1, /* CR0: n, CPL: s, PTE: s, PTE: w, ope: r */	1, /* CR0: n, CPL: s, PTE: s, PTE: w, ope: r */
Line 230 static const BYTE page_access_bit[32] =	Line 143 static const BYTE page_access_bit[32] =
1, /* CR0: p, CPL: s, PTE: u, PTE: r, ope: r */	1, /* CR0: p, CPL: s, PTE: u, PTE: r, ope: r */
0, /* CR0: p, CPL: s, PTE: u, PTE: r, ope: w */	0, /* CR0: p, CPL: s, PTE: u, PTE: r, ope: w */
1, /* CR0: p, CPL: s, PTE: u, PTE: w, ope: r */	1, /* CR0: p, CPL: s, PTE: u, PTE: w, ope: r */
0, /* CR0: p, CPL: s, PTE: u, PTE: w, ope: w */	1, /* CR0: p, CPL: s, PTE: u, PTE: w, ope: w */

0, /* CR0: p, CPL: u, PTE: s, PTE: r, ope: r */	0, /* CR0: p, CPL: u, PTE: s, PTE: r, ope: r */
0, /* CR0: p, CPL: u, PTE: s, PTE: r, ope: w */	0, /* CR0: p, CPL: u, PTE: s, PTE: r, ope: w */
Line 271 static const BYTE page_access_bit[32] =	Line 184 static const BYTE page_access_bit[32] =
* +- CR3(物理アドレス)	* +- CR3(物理アドレス)
*/	*/

static DWORD paging(DWORD laddr, int crw, int user_mode);	static UINT32 paging(UINT32 laddr, int crw, int user_mode);
static BOOL tlb_lookup(DWORD vaddr, int crw, DWORD* paddr);	#if defined(IA32_SUPPORT_TLB)
static void tlb_update(DWORD paddr, DWORD entry, int crw);	static BOOL tlb_lookup(UINT32 vaddr, int crw, UINT32 *paddr);
	static void tlb_update(UINT32 paddr, UINT entry, int crw);
	#endif


DWORD MEMCALL	UINT32 MEMCALL
cpu_linear_memory_read(DWORD laddr, DWORD length, int code)	cpu_linear_memory_read(UINT32 laddr, UINT length, int crw, int user_mode)
{	{
DWORD paddr;	UINT32 value = 0;
DWORD remain; /* page remain */	UINT32 paddr;
DWORD r;	UINT remain; /* page remain */
DWORD value = 0;	UINT r;
int crw;	int shift = 0;
int pl;

crw = CPU_PAGING_PAGE_READ;
crw \|= code ? CPU_PAGING_PAGE_CODE : CPU_PAGING_PAGE_DATA;
pl = (CPU_STAT_CPL == 3);

/* XXX: 4MB pages... */	/* XXX: 4MB pages... */
remain = 0x1000 - (laddr & 0x00000fff);	remain = 0x1000 - (laddr & 0x00000fff);
for (;;) {	for (;;) {
paddr = paging(laddr, crw, pl);	paddr = paging(laddr, crw, user_mode);

r = (remain > length) ? length : remain;	r = (remain > length) ? length : remain;
switch (r) {	switch (r) {
case 1:	case 4:
value = (value << 8) \| cpu_memoryread(paddr);	value = cpu_memoryread_d(paddr);
break;

case 2:
value = (value << 16) \| cpu_memoryread_w(paddr);
break;	break;

case 3:	case 3:
value <<= 24;	value += (UINT32)cpu_memoryread(paddr) << shift;
value \|= cpu_memoryread_w(paddr) << 8;	shift += 8;
value \|= cpu_memoryread(paddr + 2);	paddr++;
	/FALLTHROUGH/
	case 2:
	value += (UINT32)cpu_memoryread_w(paddr) << shift;
	shift += 16;
break;	break;

case 4:	case 1:
value = cpu_memoryread_d(paddr);	value += (UINT32)cpu_memoryread(paddr) << shift;
	shift += 8;
break;	break;

default:	default:
ia32_panic("cpu_linear_memory_read(): out of range\n");	ia32_panic("cpu_linear_memory_read(): out of range (r = %d)\n", r);
break;	break;
}	}

if (length == r)	length -= r;
	if (length == 0)
break;	break;

length -= r;
remain -= r;
laddr += r;	laddr += r;
	remain -= r;
	if (remain <= 0) {
	/* next page */
	remain += 0x1000;
	}
}	}

return value;	return value;
}	}

void MEMCALL	void MEMCALL
cpu_linear_memory_write(DWORD laddr, DWORD length, DWORD value)	cpu_linear_memory_write(UINT32 laddr, UINT32 value, UINT length, int user_mode)
{	{
DWORD paddr;	UINT32 paddr;
DWORD remain; /* page remain */	UINT remain; /* page remain */
DWORD r;	UINT r;
int pl;	int crw = (CPU_PAGE_WRITE\|CPU_PAGE_DATA);

pl = (CPU_STAT_CPL == 3);

/* XXX: 4MB pages... */	/* XXX: 4MB pages... */
remain = 0x1000 - (laddr & 0x00000fff);	remain = 0x1000 - (laddr & 0x00000fff);
for (;;) {	for (;;) {
paddr = paging(laddr, CPU_PAGING_PAGE_WRITE\|CPU_PAGING_PAGE_DATA, pl);	paddr = paging(laddr, crw, user_mode);

r = (remain > length) ? length : remain;	r = (remain > length) ? length : remain;
switch (r) {	switch (r) {
case 1:	case 4:
cpu_memorywrite(paddr, value);	cpu_memorywrite_d(paddr, value);
value >>= 8;
break;	break;

	case 3:
	cpu_memorywrite(paddr, value & 0xff);
	value >>= 8;
	paddr++;
	/FALLTHROUGH/
case 2:	case 2:
cpu_memorywrite_w(paddr, value);	cpu_memorywrite_w(paddr, value & 0xffff);
value >>= 16;	value >>= 16;
break;	break;

case 3:	case 1:
cpu_memorywrite_w(paddr, value);	cpu_memorywrite(paddr, value & 0xff);
cpu_memorywrite(paddr, value >> 16);	value >>= 8;
value >>= 24;
break;

case 4:
cpu_memorywrite_d(paddr, value);
break;	break;

default:	default:
ia32_panic("cpu_linear_memory_write(): out of range\n");	ia32_panic("cpu_linear_memory_write(): out of range (r = %d)\n", r);
break;	break;
}	}

if (length == r)	length -= r;
	if (length == 0)
break;	break;

length -= r;
remain -= r;
laddr += r;	laddr += r;
	remain -= r;
	if (remain <= 0) {
	/* next page */
	remain += 0x1000;
	}
}	}
}	}

void MEMCALL	void MEMCALL
paging_check(DWORD laddr, DWORD length, int rw)	paging_check(UINT32 laddr, UINT length, int crw, int user_mode)
{	{
DWORD addr;	UINT32 paddr;
int n;	UINT remain; /* page remain */
int pl;	UINT r;

pl = (CPU_STAT_CPL == 3);

/* XXX: 4MB pages... */	/* XXX: 4MB pages... */
n = ((laddr & 0xfff) + length) / 0x1000;	remain = 0x1000 - (laddr & 0x00000fff);
addr = (laddr & ~0xfff);	for (;;) {
do {	paddr = paging(laddr, crw, user_mode);
(void)paging(addr, rw, pl);
addr += 0x1000;	r = (remain > length) ? length : remain;
} while (--n > 0);
	length -= r;
	if (length == 0)
	break;

	laddr += r;
	remain -= r;
	if (remain <= 0) {
	/* next page */
	remain += 0x1000;
	}
	}
}	}

static DWORD	static UINT32
paging(DWORD laddr, int crw, int user_mode)	paging(UINT32 laddr, int crw, int user_mode)
{	{
DWORD paddr; /* physical address */	UINT32 paddr; /* physical address */
DWORD pde_addr; /* page directory entry address */	UINT32 pde_addr; /* page directory entry address */
DWORD pde; /* page directory entry */	UINT32 pde; /* page directory entry */
DWORD pte_addr; /* page table entry address */	UINT32 pte_addr; /* page table entry address */
DWORD pte; /* page table entry */	UINT32 pte; /* page table entry */
DWORD bit;	UINT bit;
DWORD err = 0;	UINT err;

#if defined(IA32_SUPPORT_TLB)	#if defined(IA32_SUPPORT_TLB)
if (tlb_lookup(laddr, crw, &paddr))	if (tlb_lookup(laddr, crw, &paddr))
return paddr;	return paddr;
#endif /* IA32_SUPPORT_TLB */	#endif /* IA32_SUPPORT_TLB */

pde_addr = (CPU_CR3 & CPU_CR3_PD_MASK) \| ((laddr >> 20) & 0xffc);	pde_addr = CPU_STAT_PDE_BASE + ((laddr >> 20) & 0xffc);
pde = cpu_memoryread_d(pde_addr);	pde = cpu_memoryread_d(pde_addr);
if (!(pde & CPU_PDE_PRESENT)) {	if (!(pde & CPU_PDE_PRESENT)) {
	VERBOSE(("paging: PTE page is not present"));
	VERBOSE(("paging: CPU_CR3 = 0x%08x", CPU_CR3));
	VERBOSE(("paging: laddr = 0x%08x, pde_addr = 0x%08x, pde = 0x%08x", laddr, pde_addr, pde));
err = 0;	err = 0;
goto pf_exception;	goto pf_exception;
}	}
Line 427 paging(DWORD laddr, int crw, int user_mo	Line 355 paging(DWORD laddr, int crw, int user_mo
cpu_memorywrite_d(pde_addr, pde);	cpu_memorywrite_d(pde_addr, pde);
}	}

	#if CPU_FAMILY >= 5
/* no support PAE */	/* no support PAE */
__ASSERT(!(CPU_CR4 & CPU_CR4_PAE));	__ASSERT(!(CPU_CR4 & CPU_CR4_PAE));

Line 438 paging(DWORD laddr, int crw, int user_mo	Line 367 paging(DWORD laddr, int crw, int user_mo
pte_addr = 0; /* compiler happy */	pte_addr = 0; /* compiler happy */

/* make physical address */	/* make physical address */
paddr = (pde & CPU_PDE_4M_BASEADDR_MASK) \| (laddr & 0x003fffff);	paddr = (pde & CPU_PDE_4M_BASEADDR_MASK) + (laddr & 0x003fffff);
} else {	} else
	#endif /* CPU_FAMILY >= 5 */
	{
/* 4KB page size */	/* 4KB page size */
pte_addr = (pde & CPU_PDE_BASEADDR_MASK) \| ((laddr >> 10) & 0xffc);	pte_addr = (pde & CPU_PDE_BASEADDR_MASK) + ((laddr >> 10) & 0xffc);
pte = cpu_memoryread_d(pte_addr);	pte = cpu_memoryread_d(pte_addr);
if (!(pte & CPU_PTE_PRESENT)) {	if (!(pte & CPU_PTE_PRESENT)) {
	VERBOSE(("paging: page is not present"));
	VERBOSE(("paging: laddr = 0x%08x, pde_addr = 0x%08x, pde = 0x%08x", laddr, pde_addr, pde));
	VERBOSE(("paging: pte_addr = 0x%08x, pte = 0x%08x", pte_addr, pte));
err = 0;	err = 0;
goto pf_exception;	goto pf_exception;
}	}
Line 453 paging(DWORD laddr, int crw, int user_mo	Line 387 paging(DWORD laddr, int crw, int user_mo
}	}

/* make physical address */	/* make physical address */
paddr = (pte & CPU_PTE_BASEADDR_MASK) \| (laddr & 0x00000fff);	paddr = (pte & CPU_PTE_BASEADDR_MASK) + (laddr & 0x00000fff);
}	}

bit = crw & 1;	bit = crw & CPU_PAGE_WRITE;
bit \|= (pde & pte & (CPU_PTE_WRITABLE\|CPU_PTE_USER_MODE));	bit \|= (pde & pte & (CPU_PTE_WRITABLE\|CPU_PTE_USER_MODE));
bit \|= (user_mode << 3);	bit \|= (user_mode << 3);
bit \|= (CPU_CR0 & CPU_CR0_WP) >> 12;	bit \|= CPU_STAT_WP;

#if !defined(USE_PAGE_ACCESS_TABLE)	#if !defined(USE_PAGE_ACCESS_TABLE)
if (!(page_access & (1 << bit)))	if (!(page_access & (1 << bit)))
Line 467 paging(DWORD laddr, int crw, int user_mo	Line 401 paging(DWORD laddr, int crw, int user_mo
if (!(page_access_bit[bit]))	if (!(page_access_bit[bit]))
#endif	#endif
{	{
	VERBOSE(("paging: page access violation."));
	VERBOSE(("paging: laddr = 0x%08x, pde_addr = 0x%08x, pde = 0x%08x", laddr, pde_addr, pde));
	VERBOSE(("paging: pte_addr = 0x%08x, pte = 0x%08x", pte_addr, pte));
	VERBOSE(("paging: paddr = 0x%08x, bit = 0x%08x", paddr, bit));
err = 1;	err = 1;
goto pf_exception;	goto pf_exception;
}	}

if ((crw & 1) && !(pte & CPU_PTE_DIRTY)) {	if ((crw & CPU_PAGE_WRITE) && !(pte & CPU_PTE_DIRTY)) {
pte \|= CPU_PTE_DIRTY;	pte \|= CPU_PTE_DIRTY;
cpu_memorywrite_d(pte_addr, pte);	cpu_memorywrite_d(pte_addr, pte);
}	}
Line 484 paging(DWORD laddr, int crw, int user_mo	Line 422 paging(DWORD laddr, int crw, int user_mo

pf_exception:	pf_exception:
CPU_CR2 = laddr;	CPU_CR2 = laddr;
err \|= ((crw & 1) << 1) \| (user_mode << 2);	err \|= ((crw & CPU_PAGE_WRITE) << 1) \| (user_mode << 2);
EXCEPTION(PF_EXCEPTION, err);	EXCEPTION(PF_EXCEPTION, err);
return 0; /* compiler happy */	return 0; /* compiler happy */
}	}
Line 494 pf_exception:	Line 432 pf_exception:
* TLB	* TLB
*/	*/
typedef struct {	typedef struct {
BYTE valid; /* TLB entry is valid */	UINT8 valid; /* TLB entry is valid */
BYTE global; /* this TLB entry is global */	UINT8 global; /* this TLB entry is global */
BYTE score;	UINT8 score;
BYTE pad;	UINT8 pad;

DWORD tag;	UINT32 tag;
DWORD mask; /* 4K or 2M or 4M */	UINT32 mask; /* 4K or 2M or 4M */

DWORD paddr; /* physical addr */	UINT32 paddr; /* physical addr */
} TLB_ENTRY_T;	} TLB_ENTRY_T;

typedef struct {	typedef struct {
BYTE kind;	UINT8 kind;
#define TLB_KIND_INSTRUCTION (1 << 1)	#define TLB_KIND_INSTRUCTION (1 << 1)
#define TLB_KIND_DATA (1 << 2)	#define TLB_KIND_DATA (1 << 2)
#define TLB_KIND_COMBINE (TLB_KIND_INSTRUCTION\|TLB_KIND_DATA)	#define TLB_KIND_COMBINE (TLB_KIND_INSTRUCTION\|TLB_KIND_DATA)
Line 514 typedef struct {	Line 452 typedef struct {
#define TLB_KIND_LARGE (1 << 4)	#define TLB_KIND_LARGE (1 << 4)
#define TLB_KIND_BOTH (TLB_KIND_SMALL\|TLB_KIND_LARGE)	#define TLB_KIND_BOTH (TLB_KIND_SMALL\|TLB_KIND_LARGE)

BYTE way; /* n-way associative */	UINT8 way; /* n-way associative */
BYTE idx; /* number of TLB index */	UINT8 idx; /* number of TLB index */
BYTE bpad;	UINT8 bpad;

WORD num; /* number of TLB entry */	UINT16 num; /* number of TLB entry */
WORD wpad;	UINT16 wpad;

TLB_ENTRY_T* entry; /* entry[assoc][idx] or entry[assoc] if idx == 1*/	TLB_ENTRY_T entry; / entry[assoc][idx] or entry[assoc] if idx == 1*/
} TLB_T;	} TLB_T;

static int ntlb;	static int ntlb;
Line 529 static TLB_T tlb[4]; /* i TLB, i (lp) TL	Line 467 static TLB_T tlb[4]; /* i TLB, i (lp) TL

#if defined(IA32_PROFILE_TLB)	#if defined(IA32_PROFILE_TLB)
/* profiling */	/* profiling */
static DWORD tlb_hits;	static UINT64 tlb_hits;
static DWORD tlb_misses;	static UINT64 tlb_misses;
static DWORD tlb_lookups;	static UINT64 tlb_lookups;
static DWORD tlb_updates;	static UINT64 tlb_updates;
static DWORD tlb_flushes;	static UINT64 tlb_flushes;
static DWORD tlb_global_flushes;	static UINT64 tlb_global_flushes;
static DWORD tlb_entry_flushes;	static UINT64 tlb_entry_flushes;

#define PROFILE_INC(v) (v)++;	#define PROFILE_INC(v) (v)++;
#else /* !IA32_PROFILE_TLB */	#else /* !IA32_PROFILE_TLB */
Line 543 static DWORD tlb_entry_flushes;	Line 481 static DWORD tlb_entry_flushes;
#endif /* IA32_PROFILE_TLB */	#endif /* IA32_PROFILE_TLB */

void	void
tlb_init()	tlb_init(void)
{	{
int i;	int i;

Line 564 tlb_init()	Line 502 tlb_init()
tlb_entry_flushes = 0;	tlb_entry_flushes = 0;
#endif /* IA32_PROFILE_TLB */	#endif /* IA32_PROFILE_TLB */

/* XXX プロセッサ種別にしたがって TLB 構成を構築する */	#if CPU_FAMILY == 4

/* とりあえず i486 形式で… */	/* とりあえず i486 形式で… */
/* combine (I/D) TLB: 4KB Pages, 4-way set associative 32 entries */	/* combine (I/D) TLB: 4KB Pages, 4-way set associative 32 entries */
ntlb = 1;	ntlb = 1;
tlb[0].kind = TLB_KIND_COMBINE \| TLB_KIND_SMALL;	tlb[0].kind = TLB_KIND_COMBINE \| TLB_KIND_SMALL;
tlb[0].num = 32;	tlb[0].num = 32;
tlb[0].way = 4;	tlb[0].way = 4;
tlb[0].idx = tlb[0].num / tlb[0].way;	#endif

for (i = 0; i < ntlb; i++) {	for (i = 0; i < ntlb; i++) {
	tlb[i].idx = tlb[i].num / tlb[i].way;

tlb[i].entry = (TLB_ENTRY_T*)calloc(sizeof(TLB_ENTRY_T), tlb[i].num);	tlb[i].entry = (TLB_ENTRY_T*)calloc(sizeof(TLB_ENTRY_T), tlb[i].num);
if (tlb[i].entry == 0) {	if (tlb[i].entry == 0) {
ia32_panic("tlb_init(): can't alloc TLB entry\n");	ia32_panic("tlb_init(): can't alloc TLB entry\n");
Line 585 tlb_init()	Line 524 tlb_init()
void	void
tlb_flush(BOOL allflush)	tlb_flush(BOOL allflush)
{	{
TLB_ENTRY_T* ep;	TLB_ENTRY_T *ep;
int i, j;	int i, j;

if (allflush) {	if (allflush) {
Line 606 tlb_flush(BOOL allflush)	Line 545 tlb_flush(BOOL allflush)
}	}

void	void
tlb_flush_page(DWORD vaddr)	tlb_flush_page(UINT32 vaddr)
{	{
TLB_ENTRY_T* ep;	TLB_ENTRY_T *ep;
int idx;	int idx;
int i;	int i;

Line 638 tlb_flush_page(DWORD vaddr)	Line 577 tlb_flush_page(DWORD vaddr)
}	}
}	}

BOOL	static BOOL
tlb_lookup(DWORD vaddr, int crw, DWORD* paddr)	tlb_lookup(UINT32 laddr, int crw, UINT32 *paddr)
{	{
TLB_ENTRY_T* ep;	TLB_ENTRY_T *ep;
int idx;	int idx;
int i;	int i;

PROFILE_INC(tlb_lookups);	PROFILE_INC(tlb_lookups);

crw &= CPU_PAGING_PAGE_CODE \| CPU_PAGING_PAGE_DATA;	crw &= CPU_PAGE_CODE \| CPU_PAGE_DATA;
for (i = 0; i < ntlb; i++) {	for (i = 0; i < ntlb; i++) {
if (tlb[i].kind & crw) {	if (tlb[i].kind & crw) {
if (tlb[i].idx == 1) {	if (tlb[i].idx == 1) {
Line 655 tlb_lookup(DWORD vaddr, int crw, DWORD*	Line 594 tlb_lookup(DWORD vaddr, int crw, DWORD*
idx = 0;	idx = 0;
} else {	} else {
if (tlb[i].kind & TLB_KIND_SMALL) {	if (tlb[i].kind & TLB_KIND_SMALL) {
idx = (vaddr >> 12) & (tlb[i].idx - 1);	idx = (laddr >> 12) & (tlb[i].idx - 1);
} else {	} else {
idx = (vaddr >> 22) & (tlb[i].idx - 1);	idx = (laddr >> 22) & (tlb[i].idx - 1);
}	}
}	}

Line 665 tlb_lookup(DWORD vaddr, int crw, DWORD*	Line 604 tlb_lookup(DWORD vaddr, int crw, DWORD*
ep = &tlb[i].entry[idx * tlb[i].way];	ep = &tlb[i].entry[idx * tlb[i].way];
for (i = 0; i < tlb[i].way; i++) {	for (i = 0; i < tlb[i].way; i++) {
if (ep->valid) {	if (ep->valid) {
if ((vaddr & ep->mask) == ep->tag) {	if ((laddr & ep->mask) == ep->tag) {
if (ep->score != (BYTE)~0)	if (ep->score != (UINT8)~0)
ep->score++;	ep->score++;
*paddr = ep->paddr;	*paddr = ep->paddr;
PROFILE_INC(tlb_hits);	PROFILE_INC(tlb_hits);
Line 680 tlb_lookup(DWORD vaddr, int crw, DWORD*	Line 619 tlb_lookup(DWORD vaddr, int crw, DWORD*
return FALSE;	return FALSE;
}	}

void	static void
tlb_update(DWORD paddr, DWORD entry, int crw)	tlb_update(UINT32 paddr, UINT entry, int crw)
{	{
TLB_ENTRY_T* ep;	TLB_ENTRY_T *ep;
int idx;	int idx;
int i, j;	int i, j;
int min_way;	int min_way;
WORD min_score = ~0;	UINT16 min_score = ~0;

PROFILE_INC(tlb_updates);	PROFILE_INC(tlb_updates);

crw &= CPU_PAGING_PAGE_CODE \| CPU_PAGING_PAGE_DATA;	crw &= CPU_PAGE_CODE \| CPU_PAGE_DATA;
for (i = 0; i < ntlb; i++) {	for (i = 0; i < ntlb; i++) {
if (tlb[i].kind & crw) {	if (tlb[i].kind & crw) {
if (tlb[i].idx == 1) {	if (tlb[i].idx == 1) {
Line 738 tlb_update(DWORD paddr, DWORD entry, int	Line 677 tlb_update(DWORD paddr, DWORD entry, int
}	}
__ASSERT(i != ntlb);	__ASSERT(i != ntlb);
}	}
#else /* !IA32_SUPPORT_TLB */
void
tlb_init()
{

/* nothing to do */
}

void
tlb_flush(BOOL allflush)
{

// UNUSED(allflush);
}

void
tlb_flush_page(DWORD vaddr)
{

// UNUSED(vaddr);
}
#endif /* IA32_SUPPORT_TLB */	#endif /* IA32_SUPPORT_TLB */

RetroPC.NET-CVS <cvs@retropc.net>

Removed from v.1.1
changed lines
	Added in v.1.12