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version 1.28, 2005/03/12 12:32:54	version 1.40, 2012/01/29 14:53:26
Line 1	Line 1
/* $Id$ */

/*	/*
* Copyright (c) 2003-2004 NONAKA Kimihiro	* Copyright (c) 2003-2004 NONAKA Kimihiro
* All rights reserved.	* All rights reserved.
Line 30	Line 28
#include "ia32.mcr"	#include "ia32.mcr"

/*	/*
* ’伊﹝扑’弁’交’孕’鬺生石瘚□	* 樍婍汙槻弁樍忴井樍巧樍唳本嗥﹜ *
* 4-31: 芺沶碧心	* 4-31: 鈭碧心
* 3: RSVD: 0 = 白巧伙玄及葆奢反芺沶申永玄啜�匹反卅井勻凶‘	* 3: RSVD: 0 = 白巧伙玄及葆奢反芺沶申永玄啜�匹反卅井勻凶‘
* 1 = 矢□斥’白巧伙玄及葆奢反﹞啜�午穴□弁今木凶 PTE 引凶反	* 1 = 矢□斥’白巧伙玄及葆奢反﹞啜�午穴□弁今木凶 PTE 引凶反
* PDE 及芺沶申永玄匏譆及丹切域勾匹﹞1 互腹請今木凶仇午匹丐月‘	* PDE 及芺沶申永玄匏譆及丹切域勾匹﹞1 互腹請今木凶仇午匹丐月‘
* 2: U/S: 0 = 白巧伙玄及葆奢午卅勻凶失弁本旦反皿伕本永扔互旦□由田奶扒’	* 2: U/S: 0 = 白巧伙玄及葆奢午卅勻凶失弁本旦反皿伕本永扔互旦□由田奶扒’
* 乒□玉匹撢墊醱卞墊歹木凶‘	* 乒□玉匹撢墊醱卞墊歹木凶‘
* 1 = 白巧伙玄及葆奢午卅勻凶失弁本旦反皿伕本永扔互交□扒’乒□玉匹	* 1 = 白巧伙玄及葆奢午卅勻凶失弁本旦反皿伕本永扔互交□扒’乒□玉匹
* 撢墊醱卞墊歹木凶‘	* 撢墊醱卞墊歹木凶‘
* 1: W/R: 0 = 白巧伙玄及葆奢午卅勻凶失弁本旦互厶心潸曰匹丐勻凶‘	* 1: W/R: 0 = 白巧伙玄及葆奢午卅勻凶失弁本旦互厶心潸曰匹丐勻凶‘
* 1 = 白巧伙玄及葆奢午卅勻凶失弁本旦互踏五慇心匹丐勻凶‘	* 1 = 白巧伙玄及葆奢午卅勻凶失弁本旦互踏五慇心匹丐勻凶‘
* 0: P: 0 = 白巧伙玄及葆奢互尕箕矢□斥匹丐勻凶‘	* 0: P: 0 = 白巧伙玄及葆奢互尕箕矢□斥匹丐勻凶‘
* 1 = 白巧伙玄及葆奢互矢□斥’伊矛伙忡賃啜�匹丐勻凶‘	* 1 = 白巧伙玄及葆奢互矢□斥’伊矛伙忡賃啜�匹丐勻凶‘
*/	*/

/*	/*
* 票摒 4.12. 矢□斥忡賃午本弘丟件玄忡賃及賺心寧歹六	* 銝 4.12. 矢□斥忡賃午本弘丟件玄忡賃及賺心寧歹六
* ＞刓 4-2. 矢□斥’犯奴伊弁玄伉午矢□斥’氾□皮伙及忡賃及賺心寧歹六＝	* ＞刓 4-2. 矢□斥’犯奴伊弁玄伉午矢□斥’氾□皮伙及忡賃及賺心寧歹六＝
*	*
* +------------+------------+------------+	* +------------+------------+------------+
* \| PDE \| PTE \| merge \|	* \| PDE \| PTE \| merge \|
Line 73	Line 71
* \| s \| rw \| s \| rw \| s \| rw \|	* \| s \| rw \| s \| rw \| s \| rw \|
* +-----+------+-----+------+-----+------+	* +-----+------+-----+------+-----+------+
*	*
* ＞奴 rw/p : CR0 ﹜石 WP ’乒’氾’生﹜乓 ON ﹜石本艭謢甲﹜穴 ro	* 蜬扔 rw/p : CR0 槦亦 WP 樍］乓樍啣∫ ON 槦亦磝巨潞啣╲槦永 ro
*/	*/

/*	/*
* ’漰銣籈＞’永’扔’弗/PxE(本篞亙扔奶本生)/CPL/CR0 ﹜生’伊﹝扑’弁’＞’永’扔’弗弁＞﹜石巨伉平弁	* 樍﹝樍＞樍尼槻＞槻永槻扔槻弗/PxE(頨湊奴剚賤翴央)/CPL/CR0 槦奴樍婍汙槻弁槻＞槻永槻扔槻弗鴘孕槦亦壚＞餑 *
* +-----+-----+-----+-----+-----+---+	* +-----+-----+-----+-----+-----+---+
* \| CR0 \| CPL \| PxE \| PxE \| ope \| \|	* \| CR0 \| CPL \| PxE \| PxE \| ope \| \|
Line 157 static const UINT8 page_access_bit[32] =	Line 155 static const UINT8 page_access_bit[32] =

/*	/*
*--	*--
* 32bit 坁咥失玉伊旦 4k 矢□斥	* 32bit 臄孕艛砍中樍脣旨槻弗 4k 樍婍汙槻弁
*	*
* ’籈甲’＞﹝仲’＞’用’孎弗	* 樍尼樍嗅中樍扔槻＞樍脣旨槻弗
* 31 22 21 12 11 0	* 31 22 21 12 11 0
* +------------------------+----------------------+--------------------------+	* +------------------------+----------------------+--------------------------+
* \| ’伊﹝扑’弁﹝仲’甘’＝’孎永’生’ \| 矢□斥’氾□皮伙 \| 左白本永玄 \|	* \| 樍婍汙槻弁樍扔樍桀丰樍乓槻永樍啣收 \| 樍婍汙槻弁樍扔樍砍汙樍极早 \| 槻尼樍忴公樍血亥 \|
* +------------------------+----------------------+--------------------------+	* +------------------------+----------------------+--------------------------+
* \| \| \|	* \| \| \|
* +-----------+ +-----------+ +----------+	* +-----------+ +-----------+ +----------+
* \| \| \|	* \| \| \|
* \| ’伊﹝扑’弁﹝仲’甘’＝’孎永’生’ \| 矢□斥’氾□皮伙矢□斥 \|	* \| 矢□斥’犯奴伊弁玄伉 \| 矢□斥’氾□皮伙矢□斥 \|
* \| +--------------------+ \| +-------------------+ +------------------+ \|	* \| +--------------------+ \| +-------------------+ +------------------+ \|
* \| \| \| \| \| \| \| \| \|	* \| \| \| \| \| \| \| \| \|
* \| \| \| \| +-------------------+ \| \| \|	* \| \| \| \| +-------------------+ \| \| \|
Line 179 static const UINT8 page_access_bit[32] =	Line 177 static const UINT8 page_access_bit[32] =
* \| \| \| \| \| \| \| \|	* \| \| \| \| \| \| \| \|
* +>+--------------------+ +>+-------------------+ +>+------------------+	* +>+--------------------+ +>+-------------------+ +>+------------------+
* \|	* \|
* +- CR3()	* +- CR3(坁咥失玉伊旦)
*/	*/

static UINT32 MEMCALL paging(const UINT32 laddr, const int ucrw) GCC_ATTR_REGPARM;	/* TLB */
#if defined(IA32_SUPPORT_TLB)	struct tlb_entry {
static void MEMCALL tlb_update(const UINT32 laddr, const UINT entry, const int ucrw) GCC_ATTR_REGPARM;	UINT32 tag; /* linear address */
#endif	#define TLB_ENTRY_TAG_VALID (1 << 0)
	/* pde & pte & CPU_PTE_WRITABLE (1 << 1) */
	/* pde & pte & CPU_PTE_USER_MODE (1 << 2) */
	#define TLB_ENTRY_TAG_DIRTY CPU_PTE_DIRTY /* (1 << 6) */
	#define TLB_ENTRY_TAG_GLOBAL CPU_PTE_GLOBAL_PAGE /* (1 << 8) */
	#define TLB_ENTRY_TAG_MAX_SHIFT 12
	UINT32 paddr; /* physical address */
	};
	static void MEMCALL tlb_update(UINT32 laddr, UINT entry, int ucrw);

	/* paging */
	static UINT32 MEMCALL paging(UINT32 laddr, int ucrw);

	/*
	* linear memory access
	*/
	/* RMW */
UINT8 MEMCALL	UINT8 MEMCALL
cpu_memory_access_la_RMW_b(UINT32 laddr, UINT32 (func)(UINT32, void ), void *arg)	cpu_memory_access_la_RMW_b(UINT32 laddr, UINT32 (CPUCALL func)(UINT32, void ), void *arg)
{	{
const int ucrw = CPU_PAGE_WRITE\|CPU_PAGE_DATA\|CPU_STAT_USER_MODE;	const int ucrw = CPU_PAGE_WRITE_DATA \| CPU_STAT_USER_MODE;
UINT32 result, value;
UINT32 paddr;	UINT32 paddr;
	UINT32 result;
	UINT8 value;

paddr = paging(laddr, ucrw);	paddr = paging(laddr, ucrw);
value = cpu_memoryread(paddr);	value = cpu_memoryread(paddr);
result = (*func)(value, arg);	result = (*func)(value, arg);
cpu_memorywrite(paddr, (UINT8)result);	cpu_memorywrite(paddr, (UINT8)result);

return value;	return value;
}	}

UINT16 MEMCALL	UINT16 MEMCALL
cpu_memory_access_la_RMW_w(UINT32 laddr, UINT32 (func)(UINT32, void ), void *arg)	cpu_memory_access_la_RMW_w(UINT32 laddr, UINT32 (CPUCALL func)(UINT32, void ), void *arg)
{	{
const int ucrw = CPU_PAGE_WRITE\|CPU_PAGE_DATA\|CPU_STAT_USER_MODE;	const int ucrw = CPU_PAGE_WRITE_DATA \| CPU_STAT_USER_MODE;
UINT32 result, value;
UINT32 paddr[2];	UINT32 paddr[2];
	UINT32 result;
	UINT16 value;

paddr[0] = paging(laddr, ucrw);	paddr[0] = paging(laddr, ucrw);
if ((laddr + 1) & 0x00000fff) {	if ((laddr + 1) & CPU_PAGE_MASK) {
value = cpu_memoryread_w(paddr[0]);	value = cpu_memoryread_w(paddr[0]);
result = (*func)(value, arg);	result = (*func)(value, arg);
cpu_memorywrite_w(paddr[0], (UINT16)result);	cpu_memorywrite_w(paddr[0], (UINT16)result);
} else {	return value;
paddr[1] = paging(laddr + 1, ucrw);
value = cpu_memoryread_b(paddr[0]);
value += (UINT16)cpu_memoryread_b(paddr[1]) << 8;
result = (*func)(value, arg);
cpu_memorywrite(paddr[0], (UINT8)result);
cpu_memorywrite(paddr[1], (UINT8)(result >> 8));
}	}

	paddr[1] = paging(laddr + 1, ucrw);
	value = cpu_memoryread_b(paddr[0]);
	value += (UINT16)cpu_memoryread_b(paddr[1]) << 8;
	result = (*func)(value, arg);
	cpu_memorywrite(paddr[0], (UINT8)result);
	cpu_memorywrite(paddr[1], (UINT8)(result >> 8));
return value;	return value;
}	}

UINT32 MEMCALL	UINT32 MEMCALL
cpu_memory_access_la_RMW_d(UINT32 laddr, UINT32 (func)(UINT32, void ), void *arg)	cpu_memory_access_la_RMW_d(UINT32 laddr, UINT32 (CPUCALL func)(UINT32, void ), void *arg)
{	{
const int ucrw = CPU_PAGE_WRITE\|CPU_PAGE_DATA\|CPU_STAT_USER_MODE;	const int ucrw = CPU_PAGE_WRITE_DATA \| CPU_STAT_USER_MODE;
UINT32 result, value;
UINT32 paddr[2];	UINT32 paddr[2];
UINT remain;	UINT32 result;
	UINT32 value;
	int remain;

paddr[0] = paging(laddr, ucrw);	paddr[0] = paging(laddr, ucrw);
remain = 0x1000 - (laddr & 0x00000fff);	remain = CPU_PAGE_SIZE - (laddr & CPU_PAGE_MASK);
if (remain >= 4) {	if (remain >= 4) {
value = cpu_memoryread_d(paddr[0]);	value = cpu_memoryread_d(paddr[0]);
result = (*func)(value, arg);	result = (*func)(value, arg);
cpu_memorywrite_d(paddr[0], result);	cpu_memorywrite_d(paddr[0], result);
} else {	return value;
paddr[1] = paging(laddr + remain, ucrw);	}
switch (remain) {
case 3:	paddr[1] = paging(laddr + remain, ucrw);
value = cpu_memoryread(paddr[0]);	switch (remain) {
value += (UINT32)cpu_memoryread_w(paddr[0] + 1) << 8;	case 3:
value += (UINT32)cpu_memoryread(paddr[1]) << 24;	value = cpu_memoryread(paddr[0]);
result = (*func)(value, arg);	value += (UINT32)cpu_memoryread_w(paddr[0] + 1) << 8;
cpu_memorywrite(paddr[0], (UINT8)result);	value += (UINT32)cpu_memoryread(paddr[1]) << 24;
cpu_memorywrite_w(paddr[0] + 1, (UINT16)(result >> 8));	result = (*func)(value, arg);
cpu_memorywrite(paddr[1], (UINT8)(result >> 24));	cpu_memorywrite(paddr[0], (UINT8)result);
break;	cpu_memorywrite_w(paddr[0] + 1, (UINT16)(result >> 8));
	cpu_memorywrite(paddr[1], (UINT8)(result >> 24));
case 2:	break;
value = cpu_memoryread_w(paddr[0]);
value += (UINT32)cpu_memoryread_w(paddr[1]) << 16;	case 2:
result = (*func)(value, arg);	value = cpu_memoryread_w(paddr[0]);
cpu_memorywrite_w(paddr[0], (UINT16)result);	value += (UINT32)cpu_memoryread_w(paddr[1]) << 16;
cpu_memorywrite_w(paddr[1], (UINT16)(result >> 16));	result = (*func)(value, arg);
break;	cpu_memorywrite_w(paddr[0], (UINT16)result);
	cpu_memorywrite_w(paddr[1], (UINT16)(result >> 16));
case 1:	break;
value = cpu_memoryread(paddr[0]);
value += (UINT32)cpu_memoryread_w(paddr[1]) << 8;	case 1:
value += (UINT32)cpu_memoryread(paddr[1] + 2) << 24;	value = cpu_memoryread(paddr[0]);
result = (*func)(value, arg);	value += (UINT32)cpu_memoryread_w(paddr[1]) << 8;
cpu_memorywrite(paddr[0], (UINT8)result);	value += (UINT32)cpu_memoryread(paddr[1] + 2) << 24;
cpu_memorywrite_w(paddr[1], (UINT16)(result >> 8));	result = (*func)(value, arg);
cpu_memorywrite(paddr[1] + 2, (UINT8)(result >> 24));	cpu_memorywrite(paddr[0], (UINT8)result);
break;	cpu_memorywrite_w(paddr[1], (UINT16)(result >> 8));
	cpu_memorywrite(paddr[1] + 2, (UINT8)(result >> 24));
default:	break;
ia32_panic("cpu_memory_access_la_RMW_d(): out of range (remain = %d)\n", remain);
return (UINT32)-1;	default:
}	ia32_panic("cpu_memory_access_la_RMW_d: out of range (remain=%d)\n", remain);
	value = 0; /* XXX compiler happy */
	break;
}	}
return value;	return value;
}	}

	/* read */
UINT8 MEMCALL	UINT8 MEMCALL
cpu_linear_memory_read_b(UINT32 laddr, const int ucrw)	cpu_linear_memory_read_b(UINT32 laddr, int ucrw)
{	{
UINT32 paddr;

paddr = paging(laddr, ucrw);	return cpu_memoryread(paging(laddr, ucrw));
return cpu_memoryread(paddr);
}	}

UINT16 MEMCALL	UINT16 MEMCALL
cpu_linear_memory_read_w(UINT32 laddr, const int ucrw)	cpu_linear_memory_read_w(UINT32 laddr, int ucrw)
{	{
UINT32 paddr[2];	UINT32 paddr[2];
UINT16 value;	UINT16 value;

paddr[0] = paging(laddr, ucrw);	paddr[0] = paging(laddr, ucrw);
if ((laddr + 1) & 0x00000fff) {	if ((laddr + 1) & CPU_PAGE_MASK)
return cpu_memoryread_w(paddr[0]);	return cpu_memoryread_w(paddr[0]);
} else {
paddr[1] = paging(laddr + 1, ucrw);	paddr[1] = paging(laddr + 1, ucrw);
value = cpu_memoryread_b(paddr[0]);	value = cpu_memoryread_b(paddr[0]);
value += (UINT16)cpu_memoryread_b(paddr[1]) << 8;	value += (UINT16)cpu_memoryread_b(paddr[1]) << 8;
return value;	return value;
}
}	}

UINT32 MEMCALL	UINT32 MEMCALL
cpu_linear_memory_read_d(UINT32 laddr, const int ucrw)	cpu_linear_memory_read_d(UINT32 laddr, int ucrw)
{	{
UINT32 paddr[2];	UINT32 paddr[2];
UINT32 value;	UINT32 value;
UINT remain;	UINT remain;

paddr[0] = paging(laddr, ucrw);	paddr[0] = paging(laddr, ucrw);
remain = 0x1000 - (laddr & 0x00000fff);	remain = CPU_PAGE_SIZE - (laddr & CPU_PAGE_MASK);
if (remain >= 4) {	if (remain >= sizeof(value))
return cpu_memoryread_d(paddr[0]);	return cpu_memoryread_d(paddr[0]);
} else {
paddr[1] = paging(laddr + remain, ucrw);	paddr[1] = paging(laddr + remain, ucrw);
switch (remain) {	switch (remain) {
case 3:	case 3:
value = cpu_memoryread(paddr[0]);	value = cpu_memoryread(paddr[0]);
value += (UINT32)cpu_memoryread_w(paddr[0] + 1) << 8;	value += (UINT32)cpu_memoryread_w(paddr[0] + 1) << 8;
value += (UINT32)cpu_memoryread(paddr[1]) << 24;	value += (UINT32)cpu_memoryread(paddr[1]) << 24;
break;	break;

case 2:	case 2:
value = cpu_memoryread_w(paddr[0]);	value = cpu_memoryread_w(paddr[0]);
value += (UINT32)cpu_memoryread_w(paddr[1]) << 16;	value += (UINT32)cpu_memoryread_w(paddr[1]) << 16;
break;	break;

case 1:	case 1:
value = cpu_memoryread(paddr[0]);	value = cpu_memoryread(paddr[0]);
value += (UINT32)cpu_memoryread_w(paddr[1]) << 8;	value += (UINT32)cpu_memoryread_w(paddr[1]) << 8;
value += (UINT32)cpu_memoryread(paddr[1] + 2) << 24;	value += (UINT32)cpu_memoryread(paddr[1] + 2) << 24;
break;	break;

default:	default:
ia32_panic("cpu_linear_memory_read_d(): out of range (remain = %d)\n", remain);	ia32_panic("cpu_linear_memory_read_d: out of range (remain=%d)\n", remain);
value = (UINT32)-1;	value = 0; /* XXX compiler happy */
break;	break;
}
return value;
}	}
	return value;
}	}

UINT64 MEMCALL	UINT64 MEMCALL
cpu_linear_memory_read_q(UINT32 laddr, const int ucrw)	cpu_linear_memory_read_q(UINT32 laddr, int ucrw)
{	{
UINT32 paddr[2];	UINT32 paddr[2];
UINT64 value;	UINT64 value;
UINT remain;	UINT remain;

paddr[0] = paging(laddr, ucrw);	paddr[0] = paging(laddr, ucrw);
remain = 0x1000 - (laddr & 0x00000fff);	remain = CPU_PAGE_SIZE - (laddr & CPU_PAGE_MASK);
if (remain >= 8) {	if (remain >= sizeof(value))
return cpu_memoryread_q(paddr[0]);	return cpu_memoryread_q(paddr[0]);
} else {
paddr[1] = paging(laddr + remain, ucrw);	paddr[1] = paging(laddr + remain, ucrw);
switch (remain) {	switch (remain) {
case 7:	case 7:
value = cpu_memoryread(paddr[0]);	value = cpu_memoryread(paddr[0]);
value += (UINT64)cpu_memoryread_w(paddr[0] + 1) << 8;	value += (UINT64)cpu_memoryread_w(paddr[0] + 1) << 8;
value += (UINT64)cpu_memoryread_d(paddr[0] + 3) << 24;	value += (UINT64)cpu_memoryread_d(paddr[0] + 3) << 24;
value += (UINT64)cpu_memoryread(paddr[1]) << 56;	value += (UINT64)cpu_memoryread(paddr[1]) << 56;
break;	break;

case 6:	case 6:
value = cpu_memoryread_w(paddr[0]);	value = cpu_memoryread_w(paddr[0]);
value += (UINT64)cpu_memoryread_d(paddr[0] + 2) << 16;	value += (UINT64)cpu_memoryread_d(paddr[0] + 2) << 16;
value += (UINT64)cpu_memoryread_w(paddr[1]) << 48;	value += (UINT64)cpu_memoryread_w(paddr[1]) << 48;
break;	break;

case 5:	case 5:
value = cpu_memoryread(paddr[0]);	value = cpu_memoryread(paddr[0]);
value += (UINT64)cpu_memoryread_d(paddr[0] + 1) << 8;	value += (UINT64)cpu_memoryread_d(paddr[0] + 1) << 8;
value += (UINT64)cpu_memoryread_w(paddr[1]) << 40;	value += (UINT64)cpu_memoryread_w(paddr[1]) << 40;
value += (UINT64)cpu_memoryread(paddr[1] + 1) << 56;	value += (UINT64)cpu_memoryread(paddr[1] + 2) << 56;
break;	break;

case 4:	case 4:
value = cpu_memoryread_d(paddr[0]);	value = cpu_memoryread_d(paddr[0]);
value += (UINT64)cpu_memoryread_d(paddr[1]) << 32;	value += (UINT64)cpu_memoryread_d(paddr[1]) << 32;
break;	break;

case 3:	case 3:
value = cpu_memoryread(paddr[0]);	value = cpu_memoryread(paddr[0]);
value += (UINT64)cpu_memoryread_w(paddr[0] + 1) << 8;	value += (UINT64)cpu_memoryread_w(paddr[0] + 1) << 8;
value += (UINT64)cpu_memoryread_d(paddr[1]) << 24;	value += (UINT64)cpu_memoryread_d(paddr[1]) << 24;
value += (UINT64)cpu_memoryread(paddr[1] + 4) << 56;	value += (UINT64)cpu_memoryread(paddr[1] + 4) << 56;
break;	break;

case 2:	case 2:
value = cpu_memoryread_w(paddr[0]);	value = cpu_memoryread_w(paddr[0]);
value += (UINT64)cpu_memoryread_d(paddr[1]) << 16;	value += (UINT64)cpu_memoryread_d(paddr[1]) << 16;
value += (UINT64)cpu_memoryread_w(paddr[1] + 4) << 48;	value += (UINT64)cpu_memoryread_w(paddr[1] + 4) << 48;
break;	break;

case 1:	case 1:
value = cpu_memoryread(paddr[0]);	value = cpu_memoryread(paddr[0]);
value += (UINT64)cpu_memoryread_d(paddr[1]) << 8;	value += (UINT64)cpu_memoryread_d(paddr[1]) << 8;
value += (UINT64)cpu_memoryread_w(paddr[1] + 4) << 40;	value += (UINT64)cpu_memoryread_w(paddr[1] + 4) << 40;
value += (UINT64)cpu_memoryread(paddr[1] + 6) << 56;	value += (UINT64)cpu_memoryread(paddr[1] + 6) << 56;
break;	break;

default:	default:
ia32_panic("cpu_linear_memory_read_q(): out of range (remain = %d)\n", remain);	ia32_panic("cpu_linear_memory_read_q: out of range (remain=%d)\n", remain);
value = (UINT64)-1;	value = 0; /* XXX compiler happy */
break;	break;
}
}	}
return value;	return value;
}	}

REG80 MEMCALL	REG80 MEMCALL
cpu_linear_memory_read_f(UINT32 laddr, const int ucrw)	cpu_linear_memory_read_f(UINT32 laddr, int ucrw)
{	{
UINT32 paddr[2];	UINT32 paddr[2];
REG80 value;	REG80 value;
Line 421 cpu_linear_memory_read_f(UINT32 laddr, c	Line 435 cpu_linear_memory_read_f(UINT32 laddr, c
UINT i, j;	UINT i, j;

paddr[0] = paging(laddr, ucrw);	paddr[0] = paging(laddr, ucrw);
remain = 0x1000 - (laddr & 0x00000fff);	remain = CPU_PAGE_SIZE - (laddr & CPU_PAGE_MASK);
if (remain >= 10) {	if (remain >= sizeof(value))
return cpu_memoryread_f(paddr[0]);	return cpu_memoryread_f(paddr[0]);
} else {
paddr[1] = paging(laddr + remain, ucrw);	paddr[1] = paging(laddr + remain, ucrw);
for (i = 0; i < remain; ++i) {	for (i = 0; i < remain; ++i) {
value.b[i] = cpu_memoryread(paddr[0] + i);	value.b[i] = cpu_memoryread(paddr[0] + i);
}
for (j = 0; i < 10; ++i, ++j) {
value.b[i] = cpu_memoryread(paddr[1] + j);
}
return value;
}	}
	for (j = 0; i < 10; ++i, ++j) {
	value.b[i] = cpu_memoryread(paddr[1] + j);
	}
	return value;
}	}

	/* write */
void MEMCALL	void MEMCALL
cpu_linear_memory_write_b(UINT32 laddr, UINT8 value, const int user_mode)	cpu_linear_memory_write_b(UINT32 laddr, UINT8 value, int ucrw)
{	{
const int ucrw = CPU_PAGE_WRITE\|CPU_PAGE_DATA\|user_mode;
UINT32 paddr;

paddr = paging(laddr, ucrw);	cpu_memorywrite(paging(laddr, ucrw), value);
cpu_memorywrite(paddr, value);
}	}

void MEMCALL	void MEMCALL
cpu_linear_memory_write_w(UINT32 laddr, UINT16 value, const int user_mode)	cpu_linear_memory_write_w(UINT32 laddr, UINT16 value, int ucrw)
{	{
const int ucrw = CPU_PAGE_WRITE\|CPU_PAGE_DATA\|user_mode;
UINT32 paddr[2];	UINT32 paddr[2];

paddr[0] = paging(laddr, ucrw);	paddr[0] = paging(laddr, ucrw);
if ((laddr + 1) & 0x00000fff) {	if ((laddr + 1) & CPU_PAGE_MASK) {
cpu_memorywrite_w(paddr[0], value);	cpu_memorywrite_w(paddr[0], value);
} else {	return;
paddr[1] = paging(laddr + 1, ucrw);
cpu_memorywrite(paddr[0], (UINT8)value);
cpu_memorywrite(paddr[1], (UINT8)(value >> 8));
}	}

	paddr[1] = paging(laddr + 1, ucrw);
	cpu_memorywrite(paddr[0], (UINT8)value);
	cpu_memorywrite(paddr[1], (UINT8)(value >> 8));
}	}

void MEMCALL	void MEMCALL
cpu_linear_memory_write_d(UINT32 laddr, UINT32 value, const int user_mode)	cpu_linear_memory_write_d(UINT32 laddr, UINT32 value, int ucrw)
{	{
const int ucrw = CPU_PAGE_WRITE\|CPU_PAGE_DATA\|user_mode;
UINT32 paddr[2];	UINT32 paddr[2];
UINT remain;	UINT remain;

paddr[0] = paging(laddr, ucrw);	paddr[0] = paging(laddr, ucrw);
remain = 0x1000 - (laddr & 0x00000fff);	remain = CPU_PAGE_SIZE - (laddr & CPU_PAGE_MASK);
if (remain >= 4) {	if (remain >= sizeof(value)) {
cpu_memorywrite_d(paddr[0], value);	cpu_memorywrite_d(paddr[0], value);
} else {	return;
paddr[1] = paging(laddr + remain, ucrw);	}
switch (remain) {
case 3:	paddr[1] = paging(laddr + remain, ucrw);
cpu_memorywrite(paddr[0], (UINT8)value);	switch (remain) {
cpu_memorywrite_w(paddr[0] + 1, (UINT16)(value >> 8));	case 3:
cpu_memorywrite(paddr[1], (UINT8)(value >> 24));	cpu_memorywrite(paddr[0], (UINT8)value);
break;	cpu_memorywrite_w(paddr[0] + 1, (UINT16)(value >> 8));
	cpu_memorywrite(paddr[1], (UINT8)(value >> 24));
case 2:	break;
cpu_memorywrite_w(paddr[0], (UINT16)value);
cpu_memorywrite_w(paddr[1], (UINT16)(value >> 16));	case 2:
break;	cpu_memorywrite_w(paddr[0], (UINT16)value);
	cpu_memorywrite_w(paddr[1], (UINT16)(value >> 16));
case 1:	break;
cpu_memorywrite(paddr[0], (UINT8)value);
cpu_memorywrite_w(paddr[1], (UINT16)(value >> 8));	case 1:
cpu_memorywrite(paddr[1] + 2, (UINT8)(value >> 24));	cpu_memorywrite(paddr[0], (UINT8)value);
break;	cpu_memorywrite_w(paddr[1], (UINT16)(value >> 8));
}	cpu_memorywrite(paddr[1] + 2, (UINT8)(value >> 24));
	break;

	default:
	ia32_panic("cpu_linear_memory_write_d: out of range (remain=%d)\n", remain);
	break;
}	}
}	}

void MEMCALL	void MEMCALL
cpu_linear_memory_write_q(UINT32 laddr, UINT64 value, const int user_mode)	cpu_linear_memory_write_q(UINT32 laddr, UINT64 value, int ucrw)
{	{
const int ucrw = CPU_PAGE_WRITE\|CPU_PAGE_DATA\|user_mode;
UINT32 paddr[2];	UINT32 paddr[2];
UINT remain;	UINT remain;

paddr[0] = paging(laddr, ucrw);	paddr[0] = paging(laddr, ucrw);
remain = 0x1000 - (laddr & 0x00000fff);	remain = CPU_PAGE_SIZE - (laddr & CPU_PAGE_MASK);
if (remain >= 8) {	if (remain >= sizeof(value)) {
cpu_memorywrite_q(paddr[0], value);	cpu_memorywrite_q(paddr[0], value);
} else {	return;
paddr[1] = paging(laddr + remain, ucrw);	}
switch (remain) {
case 7:	paddr[1] = paging(laddr + remain, ucrw);
cpu_memorywrite(paddr[0], (UINT8)value);	switch (remain) {
cpu_memorywrite_w(paddr[0] + 1, (UINT16)(value >> 8));	case 7:
cpu_memorywrite_d(paddr[0] + 3, (UINT32)(value >> 24));	cpu_memorywrite(paddr[0], (UINT8)value);
cpu_memorywrite(paddr[1], (UINT8)(value >> 56));	cpu_memorywrite_w(paddr[0] + 1, (UINT16)(value >> 8));
break;	cpu_memorywrite_d(paddr[0] + 3, (UINT32)(value >> 24));
	cpu_memorywrite(paddr[1], (UINT8)(value >> 56));
case 6:	break;
cpu_memorywrite_d(paddr[0] + 2, (UINT32)(value >> 16));
cpu_memorywrite_w(paddr[1], (UINT16)(value >> 48));	case 6:
break;	cpu_memorywrite_w(paddr[0], (UINT16)value);
	cpu_memorywrite_d(paddr[0] + 2, (UINT32)(value >> 16));
case 5:	cpu_memorywrite_w(paddr[1], (UINT16)(value >> 48));
cpu_memorywrite(paddr[0], (UINT8)value);	break;
cpu_memorywrite_d(paddr[0] + 1, (UINT32)(value >> 8));
cpu_memorywrite_w(paddr[1], (UINT16)(value >> 40));	case 5:
cpu_memorywrite(paddr[1] + 2, (UINT8)(value >> 56));	cpu_memorywrite(paddr[0], (UINT8)value);
break;	cpu_memorywrite_d(paddr[0] + 1, (UINT32)(value >> 8));
	cpu_memorywrite_w(paddr[1], (UINT16)(value >> 40));
case 4:	cpu_memorywrite(paddr[1] + 2, (UINT8)(value >> 56));
cpu_memorywrite_d(paddr[0], (UINT32)value);	break;
cpu_memorywrite_d(paddr[1], (UINT32)(value >> 32));
break;	case 4:
	cpu_memorywrite_d(paddr[0], (UINT32)value);
case 3:	cpu_memorywrite_d(paddr[1], (UINT32)(value >> 32));
cpu_memorywrite(paddr[0], (UINT8)value);	break;
cpu_memorywrite_w(paddr[0] + 1, (UINT16)(value >> 8));
cpu_memorywrite_d(paddr[1], (UINT32)(value >> 24));	case 3:
cpu_memorywrite(paddr[1] + 4, (UINT8)(value >> 56));	cpu_memorywrite(paddr[0], (UINT8)value);
break;	cpu_memorywrite_w(paddr[0] + 1, (UINT16)(value >> 8));
	cpu_memorywrite_d(paddr[1], (UINT32)(value >> 24));
case 2:	cpu_memorywrite(paddr[1] + 4, (UINT8)(value >> 56));
cpu_memorywrite_w(paddr[0], (UINT16)value);	break;
cpu_memorywrite_d(paddr[1], (UINT32)(value >> 16));
cpu_memorywrite_w(paddr[1] + 4, (UINT16)(value >> 48));	case 2:
break;	cpu_memorywrite_w(paddr[0], (UINT16)value);
	cpu_memorywrite_d(paddr[1], (UINT32)(value >> 16));
case 1:	cpu_memorywrite_w(paddr[1] + 4, (UINT16)(value >> 48));
cpu_memorywrite(paddr[0], (UINT8)value);	break;
cpu_memorywrite_d(paddr[1], (UINT32)(value >> 8));
cpu_memorywrite_w(paddr[1] + 4, (UINT16)(value >> 40));	case 1:
cpu_memorywrite(paddr[1] + 6, (UINT8)(value >> 56));	cpu_memorywrite(paddr[0], (UINT8)value);
break;	cpu_memorywrite_d(paddr[1], (UINT32)(value >> 8));
}	cpu_memorywrite_w(paddr[1] + 4, (UINT16)(value >> 40));
	cpu_memorywrite(paddr[1] + 6, (UINT8)(value >> 56));
	break;

	default:
	ia32_panic("cpu_linear_memory_write_q: out of range (remain=%d)\n", remain);
	break;
}	}
}	}

void MEMCALL	void MEMCALL
cpu_linear_memory_write_f(UINT32 laddr, const REG80 *value, const int user_mode)	cpu_linear_memory_write_f(UINT32 laddr, const REG80 *value, int ucrw)
{	{
const int ucrw = CPU_PAGE_WRITE\|CPU_PAGE_DATA\|user_mode;
UINT32 paddr[2];	UINT32 paddr[2];
UINT remain;	UINT remain;
UINT i, j;	UINT i, j;

paddr[0] = paging(laddr, ucrw);	paddr[0] = paging(laddr, ucrw);
remain = 0x1000 - (laddr & 0x00000fff);	remain = CPU_PAGE_SIZE - (laddr & CPU_PAGE_MASK);
if (remain >= 10) {	if (remain >= sizeof(value)) {
cpu_memorywrite_f(paddr[0], value);	cpu_memorywrite_f(paddr[0], value);
} else {	return;
paddr[1] = paging(laddr + remain, ucrw);
for (i = 0; i < remain; ++i) {
cpu_memorywrite(paddr[0] + i, value->b[i]);
}
for (j = 0; i < 10; ++i, ++j) {
cpu_memorywrite(paddr[1] + j, value->b[i]);
}
}	}
}

	paddr[1] = paging(laddr + remain, ucrw);
	for (i = 0; i < remain; ++i) {
	cpu_memorywrite(paddr[0] + i, value->b[i]);
	}
	for (j = 0; i < 10; ++i, ++j) {
	cpu_memorywrite(paddr[1] + j, value->b[i]);
	}
	}

	/*
	* linear address memory access function
	*/
void MEMCALL	void MEMCALL
cpu_memory_access_la_region(UINT32 laddr, UINT length, const int ucrw, BYTE *data)	cpu_memory_access_la_region(UINT32 laddr, UINT length, int ucrw, UINT8 *data)
{	{
UINT32 paddr;	UINT32 paddr;
UINT remain; /* page remain */	UINT remain; /* page remain */
UINT r;	UINT r;

if (length == 0)	while (length > 0) {
return;	remain = CPU_PAGE_SIZE - (laddr & CPU_PAGE_MASK);

remain = 0x1000 - (laddr & 0x00000fff);
for (;;) {
if (!CPU_STAT_PAGING) {	if (!CPU_STAT_PAGING) {
paddr = laddr;	paddr = laddr;
} else {	} else {
Line 606 cpu_memory_access_la_region(UINT32 laddr	Line 625 cpu_memory_access_la_region(UINT32 laddr
cpu_memorywrite_region(paddr, data, r);	cpu_memorywrite_region(paddr, data, r);
}	}

length -= r;
if (length == 0)
break;

data += r;
laddr += r;	laddr += r;
remain -= r;	data += r;
if (remain <= 0) {	length -= r;
/* next page */
remain += 0x1000;
}
}	}
}	}

void MEMCALL	UINT32 MEMCALL
paging_check(UINT32 laddr, UINT length, const int ucrw)	laddr2paddr(UINT32 laddr, int ucrw)
{	{
UINT32 paddr;
UINT remain; /* page remain */
UINT r;

remain = 0x1000 - (laddr & 0x00000fff);
for (;;) {
paddr = paging(laddr, ucrw);

r = (remain > length) ? length : remain;

length -= r;	return paging(laddr, ucrw);
if (length == 0)
break;

laddr += r;
remain -= r;
if (remain <= 0) {
/* next page */
remain += 0x1000;
}
}
}	}

	/*
	* paging
	*/
static UINT32 MEMCALL	static UINT32 MEMCALL
paging(const UINT32 laddr, const int ucrw)	paging(UINT32 laddr, int ucrw)
{	{
	struct tlb_entry *ep;
UINT32 paddr; /* physical address */	UINT32 paddr; /* physical address */
UINT32 pde_addr; /* page directory entry address */	UINT32 pde_addr; /* page directory entry address */
UINT32 pde; /* page directory entry */	UINT32 pde; /* page directory entry */
Line 656 paging(const UINT32 laddr, const int ucr	Line 652 paging(const UINT32 laddr, const int ucr
UINT32 pte; /* page table entry */	UINT32 pte; /* page table entry */
UINT bit;	UINT bit;
UINT err;	UINT err;
#if defined(IA32_SUPPORT_TLB)
TLB_ENTRY_T *ep;

ep = tlb_lookup(laddr, ucrw);	ep = tlb_lookup(laddr, ucrw);
if (ep != NULL)	if (ep != NULL)
return ep->paddr + (laddr & 0xfff);	return ep->paddr + (laddr & CPU_PAGE_MASK);
#endif

pde_addr = CPU_STAT_PDE_BASE + ((laddr >> 20) & 0xffc);	pde_addr = CPU_STAT_PDE_BASE + ((laddr >> 20) & 0xffc);
pde = cpu_memoryread_d(pde_addr);	pde = cpu_memoryread_d(pde_addr);
Line 693 paging(const UINT32 laddr, const int ucr	Line 686 paging(const UINT32 laddr, const int ucr
}	}

/* make physical address */	/* make physical address */
paddr = (pte & CPU_PTE_BASEADDR_MASK) + (laddr & 0x00000fff);	paddr = (pte & CPU_PTE_BASEADDR_MASK) + (laddr & CPU_PAGE_MASK);

bit = ucrw & (CPU_PAGE_WRITE\|CPU_PAGE_USER_MODE);	bit = ucrw & (CPU_PAGE_WRITE\|CPU_PAGE_USER_MODE);
bit \|= (pde & pte & (CPU_PTE_WRITABLE\|CPU_PTE_USER_MODE));	bit \|= (pde & pte & (CPU_PTE_WRITABLE\|CPU_PTE_USER_MODE));
Line 718 paging(const UINT32 laddr, const int ucr	Line 711 paging(const UINT32 laddr, const int ucr
cpu_memorywrite_d(pte_addr, pte);	cpu_memorywrite_d(pte_addr, pte);
}	}

#if defined(IA32_SUPPORT_TLB)	tlb_update(laddr, pte, (bit & (CPU_PTE_WRITABLE\|CPU_PTE_USER_MODE)) + ((ucrw & CPU_PAGE_CODE) ? 1 : 0));
tlb_update(laddr, pte, (bit & (CPU_PTE_WRITABLE\|CPU_PTE_USER_MODE)) + ((ucrw & CPU_PAGE_CODE) >> 1));
#endif
return paddr;	return paddr;

pf_exception:	pf_exception:
Line 731 pf_exception:	Line 723 pf_exception:
return 0; /* compiler happy */	return 0; /* compiler happy */
}	}


#if defined(IA32_SUPPORT_TLB)
/*	/*
* TLB	* TLB
*/	*/
#define TLB_GET_PADDR(ep, addr) ((ep)->paddr + ((addr) & ~CPU_PTE_BASEADDR_MASK))
#define TLB_SET_PADDR(ep, addr) ((ep)->paddr = (addr) & CPU_PTE_BASEADDR_MASK)

#define TLB_TAG_SHIFT TLB_ENTRY_TAG_MAX_SHIFT	#define TLB_TAG_SHIFT TLB_ENTRY_TAG_MAX_SHIFT
#define TLB_TAG_MASK (~((1 << TLB_TAG_SHIFT) - 1))	#define TLB_TAG_MASK (~((1 << TLB_TAG_SHIFT) - 1))
#define TLB_GET_TAG_ADDR(ep) ((ep)->tag & TLB_TAG_MASK)	#define TLB_GET_TAG_ADDR(ep) ((ep)->tag & TLB_TAG_MASK)
Line 758 do { \	Line 745 do { \
#if (CPU_FEATURES & CPU_FEATURE_PGE) == CPU_FEATURE_PGE	#if (CPU_FEATURES & CPU_FEATURE_PGE) == CPU_FEATURE_PGE
#define TLB_IS_GLOBAL(ep) ((ep)->tag & TLB_ENTRY_TAG_GLOBAL)	#define TLB_IS_GLOBAL(ep) ((ep)->tag & TLB_ENTRY_TAG_GLOBAL)
#else	#else
#define TLB_IS_GLOBAL(ep) FALSE	#define TLB_IS_GLOBAL(ep) 0
#endif	#endif

#define TLB_SET_TAG_FLAGS(ep, entry, bit) \	#define TLB_SET_TAG_FLAGS(ep, entry, bit) \
Line 773 do { \	Line 760 do { \
#define TLB_ENTRY_MASK (NENTRY - 1)	#define TLB_ENTRY_MASK (NENTRY - 1)

typedef struct {	typedef struct {
TLB_ENTRY_T entry[NENTRY];	struct tlb_entry entry[NENTRY];
} TLB_T;	} tlb_t;
	static tlb_t tlb[NTLB];
static TLB_T tlb[NTLB];

#if defined(IA32_PROFILE_TLB)
/* profiling */
typedef struct {
UINT64 tlb_hits;
UINT64 tlb_misses;
UINT64 tlb_lookups;
UINT64 tlb_updates;
UINT64 tlb_flushes;
UINT64 tlb_global_flushes;
UINT64 tlb_entry_flushes;
} TLB_PROFILE_T;

static TLB_PROFILE_T tlb_profile;

#define PROFILE_INC(v) tlb_profile.v++
#else /* !IA32_PROFILE_TLB */
#define PROFILE_INC(v)
#endif /* IA32_PROFILE_TLB */


void	void
tlb_init(void)	tlb_init(void)
{	{

memset(tlb, 0, sizeof(tlb));	memset(tlb, 0, sizeof(tlb));
#if defined(IA32_PROFILE_TLB)
memset(tlb_profile, 0, sizeof(tlb_profile));
#endif /* IA32_PROFILE_TLB */
}	}

void MEMCALL	void MEMCALL
tlb_flush(BOOL allflush)	tlb_flush(BOOL allflush)
{	{
TLB_ENTRY_T *ep;	struct tlb_entry *ep;
int i;	int i;
int n;	int n;

if (allflush) {	if (allflush) {
PROFILE_INC(tlb_global_flushes);	tlb_init();
} else {	return;
PROFILE_INC(tlb_flushes);
}	}

for (n = 0; n < NTLB; n++) {	for (n = 0; n < NTLB; n++) {
for (i = 0; i < NENTRY ; i++) {	for (i = 0; i < NENTRY ; i++) {
ep = &tlb[n].entry[i];	ep = &tlb[n].entry[i];
if (TLB_IS_VALID(ep) && (allflush \|\| !TLB_IS_GLOBAL(ep))) {	if (TLB_IS_VALID(ep) && !TLB_IS_GLOBAL(ep)) {
TLB_SET_INVALID(ep);	TLB_SET_INVALID(ep);
PROFILE_INC(tlb_entry_flushes);
}	}
}	}
}	}
Line 835 tlb_flush(BOOL allflush)	Line 796 tlb_flush(BOOL allflush)
void MEMCALL	void MEMCALL
tlb_flush_page(UINT32 laddr)	tlb_flush_page(UINT32 laddr)
{	{
TLB_ENTRY_T *ep;	struct tlb_entry *ep;
int idx;	int idx;
int n;	int n;

PROFILE_INC(tlb_flushes);

idx = (laddr >> TLB_ENTRY_SHIFT) & TLB_ENTRY_MASK;	idx = (laddr >> TLB_ENTRY_SHIFT) & TLB_ENTRY_MASK;

for (n = 0; n < NTLB; n++) {	for (n = 0; n < NTLB; n++) {
Line 848 tlb_flush_page(UINT32 laddr)	Line 807 tlb_flush_page(UINT32 laddr)
if (TLB_IS_VALID(ep)) {	if (TLB_IS_VALID(ep)) {
if ((laddr & TLB_TAG_MASK) == TLB_GET_TAG_ADDR(ep)) {	if ((laddr & TLB_TAG_MASK) == TLB_GET_TAG_ADDR(ep)) {
TLB_SET_INVALID(ep);	TLB_SET_INVALID(ep);
PROFILE_INC(tlb_entry_flushes);
}	}
}	}
}	}
}	}

TLB_ENTRY_T * MEMCALL	struct tlb_entry * MEMCALL
tlb_lookup(const UINT32 laddr, const int ucrw)	tlb_lookup(UINT32 laddr, int ucrw)
{	{
TLB_ENTRY_T *ep;	struct tlb_entry *ep;
UINT bit;	UINT bit;
int idx;	int idx;
int n;	int n;

PROFILE_INC(tlb_lookups);	n = (ucrw & CPU_PAGE_CODE) ? 1 : 0;

n = (ucrw & CPU_PAGE_CODE) >> 1;
idx = (laddr >> TLB_ENTRY_SHIFT) & TLB_ENTRY_MASK;	idx = (laddr >> TLB_ENTRY_SHIFT) & TLB_ENTRY_MASK;
ep = &tlb[n].entry[idx];	ep = &tlb[n].entry[idx];

Line 880 tlb_lookup(const UINT32 laddr, const int	Line 836 tlb_lookup(const UINT32 laddr, const int
#endif	#endif
{	{
if (!(ucrw & CPU_PAGE_WRITE) \|\| TLB_IS_DIRTY(ep)) {	if (!(ucrw & CPU_PAGE_WRITE) \|\| TLB_IS_DIRTY(ep)) {
PROFILE_INC(tlb_hits);
return ep;	return ep;
}	}
}	}
}	}
}	}
PROFILE_INC(tlb_misses);
return NULL;	return NULL;
}	}

static void MEMCALL	static void MEMCALL
tlb_update(const UINT32 laddr, const UINT entry, const int bit)	tlb_update(UINT32 laddr, UINT entry, int bit)
{	{
TLB_ENTRY_T *ep;	struct tlb_entry *ep;
UINT32 pos;
int idx;	int idx;
int n;	int n;

PROFILE_INC(tlb_updates);

n = bit & 1;	n = bit & 1;
idx = (laddr >> TLB_ENTRY_SHIFT) & TLB_ENTRY_MASK;	idx = (laddr >> TLB_ENTRY_SHIFT) & TLB_ENTRY_MASK;
ep = &tlb[n].entry[idx];	ep = &tlb[n].entry[idx];

TLB_SET_VALID(ep);	TLB_SET_VALID(ep);
TLB_SET_TAG_ADDR(ep, laddr);	TLB_SET_TAG_ADDR(ep, laddr);
TLB_SET_PADDR(ep, entry);
TLB_SET_TAG_FLAGS(ep, entry, bit);	TLB_SET_TAG_FLAGS(ep, entry, bit);
	ep->paddr = entry & CPU_PTE_BASEADDR_MASK;
if (ep->paddr < CPU_MEMREADMAX) {
ep->memp = mem + ep->paddr;
return;
} else if (ep->paddr >= USE_HIMEM) {
pos = (ep->paddr & CPU_ADRSMASK) - 0x100000;
if (pos < CPU_EXTMEMSIZE) {
ep->memp = CPU_EXTMEM + pos;
return;
}
}
ep->memp = NULL;
}	}
#endif /* IA32_SUPPORT_TLB */

RetroPC.NET-CVS <cvs@retropc.net>

Removed from v.1.28
changed lines
	Added in v.1.40