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version 1.29, 2007/02/06 14:20:57	version 1.34, 2011/12/21 18:07:57
Line 1	Line 1
/* $Id$ */

/*	/*
* Copyright (c) 2003-2004 NONAKA Kimihiro	* Copyright (c) 2003-2004 NONAKA Kimihiro
* All rights reserved.	* All rights reserved.
Line 30	Line 28
#include "ia32.mcr"	#include "ia32.mcr"

/*	/*
* ’伊﹝扑’弁’交’孕’鬺生石瘚□	* 樍婍汙槻弁樍忴井樍巧樍唳本嗥﹜ *
* 4-31: 芺沶碧心	* 4-31: 鈭碧心
* 3: RSVD: 0 = 白巧伙玄及葆奢反芺沶申永玄啜�匹反卅井勻凶‘	* 3: RSVD: 0 = 白巧伙玄及葆奢反芺沶申永玄啜�匹反卅井勻凶‘
* 1 = 矢□斥’白巧伙玄及葆奢反﹞啜�午穴□弁今木凶 PTE 引凶反	* 1 = 矢□斥’白巧伙玄及葆奢反﹞啜�午穴□弁今木凶 PTE 引凶反
* PDE 及芺沶申永玄匏譆及丹切域勾匹﹞1 互腹請今木凶仇午匹丐月‘	* PDE 及芺沶申永玄匏譆及丹切域勾匹﹞1 互腹請今木凶仇午匹丐月‘
* 2: U/S: 0 = 白巧伙玄及葆奢午卅勻凶失弁本旦反皿伕本永扔互旦□由田奶扒’	* 2: U/S: 0 = 白巧伙玄及葆奢午卅勻凶失弁本旦反皿伕本永扔互旦□由田奶扒’
* 乒□玉匹撢墊醱卞墊歹木凶‘	* 乒□玉匹撢墊醱卞墊歹木凶‘
* 1 = 白巧伙玄及葆奢午卅勻凶失弁本旦反皿伕本永扔互交□扒’乒□玉匹	* 1 = 白巧伙玄及葆奢午卅勻凶失弁本旦反皿伕本永扔互交□扒’乒□玉匹
* 撢墊醱卞墊歹木凶‘	* 撢墊醱卞墊歹木凶‘
* 1: W/R: 0 = 白巧伙玄及葆奢午卅勻凶失弁本旦互厶心潸曰匹丐勻凶‘	* 1: W/R: 0 = 白巧伙玄及葆奢午卅勻凶失弁本旦互厶心潸曰匹丐勻凶‘
* 1 = 白巧伙玄及葆奢午卅勻凶失弁本旦互踏五慇心匹丐勻凶‘	* 1 = 白巧伙玄及葆奢午卅勻凶失弁本旦互踏五慇心匹丐勻凶‘
* 0: P: 0 = 白巧伙玄及葆奢互尕箕矢□斥匹丐勻凶‘	* 0: P: 0 = 白巧伙玄及葆奢互尕箕矢□斥匹丐勻凶‘
* 1 = 白巧伙玄及葆奢互矢□斥’伊矛伙忡賃啜�匹丐勻凶‘	* 1 = 白巧伙玄及葆奢互矢□斥’伊矛伙忡賃啜�匹丐勻凶‘
*/	*/

/*	/*
* 票摒 4.12. 矢□斥忡賃午本弘丟件玄忡賃及賺心寧歹六	* 銝 4.12. 矢□斥忡賃午本弘丟件玄忡賃及賺心寧歹六
* ＞刓 4-2. 矢□斥’犯奴伊弁玄伉午矢□斥’氾□皮伙及忡賃及賺心寧歹六＝	* ＞刓 4-2. 矢□斥’犯奴伊弁玄伉午矢□斥’氾□皮伙及忡賃及賺心寧歹六＝
*	*
* +------------+------------+------------+	* +------------+------------+------------+
* \| PDE \| PTE \| merge \|	* \| PDE \| PTE \| merge \|
Line 73	Line 71
* \| s \| rw \| s \| rw \| s \| rw \|	* \| s \| rw \| s \| rw \| s \| rw \|
* +-----+------+-----+------+-----+------+	* +-----+------+-----+------+-----+------+
*	*
* ＞奴 rw/p : CR0 ﹜石 WP ’乒’氾’生﹜乓 ON ﹜石本艭謢甲﹜穴 ro	* 蜬扔 rw/p : CR0 槦亦 WP 樍］乓樍啣∫ ON 槦亦磝巨潞啣╲槦永 ro
*/	*/

/*	/*
* ’漰銣籈＞’永’扔’弗/PxE(本篞亙扔奶本生)/CPL/CR0 ﹜生’伊﹝扑’弁’＞’永’扔’弗弁＞﹜石巨伉平弁	* 樍﹝樍＞樍尼槻＞槻永槻扔槻弗/PxE(頨湊奴剚賤翴央)/CPL/CR0 槦奴樍婍汙槻弁槻＞槻永槻扔槻弗鴘孕槦亦壚＞餑 *
* +-----+-----+-----+-----+-----+---+	* +-----+-----+-----+-----+-----+---+
* \| CR0 \| CPL \| PxE \| PxE \| ope \| \|	* \| CR0 \| CPL \| PxE \| PxE \| ope \| \|
Line 157 static const UINT8 page_access_bit[32] =	Line 155 static const UINT8 page_access_bit[32] =

/*	/*
*--	*--
* 32bit 坁咥失玉伊旦 4k 矢□斥	* 32bit 臄孕艛砍中樍脣旨槻弗 4k 樍婍汙槻弁
*	*
* ’籈甲’＞﹝仲’＞’用’孎弗	* 樍尼樍嗅中樍扔槻＞樍脣旨槻弗
* 31 22 21 12 11 0	* 31 22 21 12 11 0
* +------------------------+----------------------+--------------------------+	* +------------------------+----------------------+--------------------------+
* \| ’伊﹝扑’弁﹝仲’甘’＝’孎永’生’ \| 矢□斥’氾□皮伙 \| 左白本永玄 \|	* \| 樍婍汙槻弁樍扔樍桀丰樍乓槻永樍啣收 \| 樍婍汙槻弁樍扔樍砍汙樍极早 \| 槻尼樍忴公樍血亥 \|
* +------------------------+----------------------+--------------------------+	* +------------------------+----------------------+--------------------------+
* \| \| \|	* \| \| \|
* +-----------+ +-----------+ +----------+	* +-----------+ +-----------+ +----------+
* \| \| \|	* \| \| \|
* \| ’伊﹝扑’弁﹝仲’甘’＝’孎永’生’ \| 矢□斥’氾□皮伙矢□斥 \|	* \| 矢□斥’犯奴伊弁玄伉 \| 矢□斥’氾□皮伙矢□斥 \|
* \| +--------------------+ \| +-------------------+ +------------------+ \|	* \| +--------------------+ \| +-------------------+ +------------------+ \|
* \| \| \| \| \| \| \| \| \|	* \| \| \| \| \| \| \| \| \|
* \| \| \| \| +-------------------+ \| \| \|	* \| \| \| \| +-------------------+ \| \| \|
Line 179 static const UINT8 page_access_bit[32] =	Line 177 static const UINT8 page_access_bit[32] =
* \| \| \| \| \| \| \| \|	* \| \| \| \| \| \| \| \|
* +>+--------------------+ +>+-------------------+ +>+------------------+	* +>+--------------------+ +>+-------------------+ +>+------------------+
* \|	* \|
* +- CR3()	* +- CR3(坁咥失玉伊旦)
*/	*/

static UINT32 MEMCALL paging(const UINT32 laddr, const int ucrw);	static UINT32 MEMCALL paging(const UINT32 laddr, const int ucrw);
#if defined(IA32_SUPPORT_TLB)
static void MEMCALL tlb_update(const UINT32 laddr, const UINT entry, const int ucrw);	static void MEMCALL tlb_update(const UINT32 laddr, const UINT entry, const int ucrw);
#endif
	#define PAGE_SIZE 0x1000
	#define PAGE_MASK (PAGE_SIZE - 1)

UINT8 MEMCALL	UINT8 MEMCALL
cpu_memory_access_la_RMW_b(UINT32 laddr, UINT32 (func)(UINT32, void ), void *arg)	cpu_memory_access_la_RMW_b(UINT32 laddr, UINT32 (func)(UINT32, void ), void *arg)
{	{
const int ucrw = CPU_PAGE_WRITE\|CPU_PAGE_DATA\|CPU_STAT_USER_MODE;	const int ucrw = CPU_PAGE_WRITE_DATA\|CPU_STAT_USER_MODE;
UINT32 result, value;	UINT32 result, value;
UINT32 paddr;	UINT32 paddr;

Line 205 cpu_memory_access_la_RMW_b(UINT32 laddr,	Line 204 cpu_memory_access_la_RMW_b(UINT32 laddr,
UINT16 MEMCALL	UINT16 MEMCALL
cpu_memory_access_la_RMW_w(UINT32 laddr, UINT32 (func)(UINT32, void ), void *arg)	cpu_memory_access_la_RMW_w(UINT32 laddr, UINT32 (func)(UINT32, void ), void *arg)
{	{
const int ucrw = CPU_PAGE_WRITE\|CPU_PAGE_DATA\|CPU_STAT_USER_MODE;	const int ucrw = CPU_PAGE_WRITE_DATA\|CPU_STAT_USER_MODE;
UINT32 result, value;	UINT32 result, value;
UINT32 paddr[2];	UINT32 paddr[2];

paddr[0] = paging(laddr, ucrw);	paddr[0] = paging(laddr, ucrw);
if ((laddr + 1) & 0x00000fff) {	if ((laddr + 1) & PAGE_MASK) {
value = cpu_memoryread_w(paddr[0]);	value = cpu_memoryread_w(paddr[0]);
result = (*func)(value, arg);	result = (*func)(value, arg);
cpu_memorywrite_w(paddr[0], (UINT16)result);	cpu_memorywrite_w(paddr[0], (UINT16)result);
Line 228 cpu_memory_access_la_RMW_w(UINT32 laddr,	Line 227 cpu_memory_access_la_RMW_w(UINT32 laddr,
UINT32 MEMCALL	UINT32 MEMCALL
cpu_memory_access_la_RMW_d(UINT32 laddr, UINT32 (func)(UINT32, void ), void *arg)	cpu_memory_access_la_RMW_d(UINT32 laddr, UINT32 (func)(UINT32, void ), void *arg)
{	{
const int ucrw = CPU_PAGE_WRITE\|CPU_PAGE_DATA\|CPU_STAT_USER_MODE;	const int ucrw = CPU_PAGE_WRITE_DATA\|CPU_STAT_USER_MODE;
UINT32 result, value;	UINT32 result, value;
UINT32 paddr[2];	UINT32 paddr[2];
UINT remain;	UINT remain;

paddr[0] = paging(laddr, ucrw);	paddr[0] = paging(laddr, ucrw);
remain = 0x1000 - (laddr & 0x00000fff);	remain = PAGE_SIZE - (laddr & PAGE_MASK);
if (remain >= 4) {	if (remain >= 4) {
value = cpu_memoryread_d(paddr[0]);	value = cpu_memoryread_d(paddr[0]);
result = (*func)(value, arg);	result = (*func)(value, arg);
Line 294 cpu_linear_memory_read_w(UINT32 laddr, c	Line 293 cpu_linear_memory_read_w(UINT32 laddr, c
UINT16 value;	UINT16 value;

paddr[0] = paging(laddr, ucrw);	paddr[0] = paging(laddr, ucrw);
if ((laddr + 1) & 0x00000fff) {	if ((laddr + 1) & PAGE_MASK) {
return cpu_memoryread_w(paddr[0]);	return cpu_memoryread_w(paddr[0]);
} else {	} else {
paddr[1] = paging(laddr + 1, ucrw);	paddr[1] = paging(laddr + 1, ucrw);
Line 312 cpu_linear_memory_read_d(UINT32 laddr, c	Line 311 cpu_linear_memory_read_d(UINT32 laddr, c
UINT remain;	UINT remain;

paddr[0] = paging(laddr, ucrw);	paddr[0] = paging(laddr, ucrw);
remain = 0x1000 - (laddr & 0x00000fff);	remain = PAGE_SIZE - (laddr & PAGE_MASK);
if (remain >= 4) {	if (remain >= 4) {
return cpu_memoryread_d(paddr[0]);	return cpu_memoryread_d(paddr[0]);
} else {	} else {
Line 352 cpu_linear_memory_read_q(UINT32 laddr, c	Line 351 cpu_linear_memory_read_q(UINT32 laddr, c
UINT remain;	UINT remain;

paddr[0] = paging(laddr, ucrw);	paddr[0] = paging(laddr, ucrw);
remain = 0x1000 - (laddr & 0x00000fff);	remain = PAGE_SIZE - (laddr & PAGE_MASK);
if (remain >= 8) {	if (remain >= 8) {
return cpu_memoryread_q(paddr[0]);	return cpu_memoryread_q(paddr[0]);
} else {	} else {
Line 375 cpu_linear_memory_read_q(UINT32 laddr, c	Line 374 cpu_linear_memory_read_q(UINT32 laddr, c
value = cpu_memoryread(paddr[0]);	value = cpu_memoryread(paddr[0]);
value += (UINT64)cpu_memoryread_d(paddr[0] + 1) << 8;	value += (UINT64)cpu_memoryread_d(paddr[0] + 1) << 8;
value += (UINT64)cpu_memoryread_w(paddr[1]) << 40;	value += (UINT64)cpu_memoryread_w(paddr[1]) << 40;
value += (UINT64)cpu_memoryread(paddr[1] + 1) << 56;	value += (UINT64)cpu_memoryread(paddr[1] + 2) << 56;
break;	break;

case 4:	case 4:
Line 421 cpu_linear_memory_read_f(UINT32 laddr, c	Line 420 cpu_linear_memory_read_f(UINT32 laddr, c
UINT i, j;	UINT i, j;

paddr[0] = paging(laddr, ucrw);	paddr[0] = paging(laddr, ucrw);
remain = 0x1000 - (laddr & 0x00000fff);	remain = PAGE_SIZE - (laddr & PAGE_MASK);
if (remain >= 10) {	if (remain >= 10) {
return cpu_memoryread_f(paddr[0]);	return cpu_memoryread_f(paddr[0]);
} else {	} else {
Line 439 cpu_linear_memory_read_f(UINT32 laddr, c	Line 438 cpu_linear_memory_read_f(UINT32 laddr, c
void MEMCALL	void MEMCALL
cpu_linear_memory_write_b(UINT32 laddr, UINT8 value, const int user_mode)	cpu_linear_memory_write_b(UINT32 laddr, UINT8 value, const int user_mode)
{	{
const int ucrw = CPU_PAGE_WRITE\|CPU_PAGE_DATA\|user_mode;	const int ucrw = CPU_PAGE_WRITE_DATA\|user_mode;
UINT32 paddr;	UINT32 paddr;

paddr = paging(laddr, ucrw);	paddr = paging(laddr, ucrw);
Line 449 cpu_linear_memory_write_b(UINT32 laddr,	Line 448 cpu_linear_memory_write_b(UINT32 laddr,
void MEMCALL	void MEMCALL
cpu_linear_memory_write_w(UINT32 laddr, UINT16 value, const int user_mode)	cpu_linear_memory_write_w(UINT32 laddr, UINT16 value, const int user_mode)
{	{
const int ucrw = CPU_PAGE_WRITE\|CPU_PAGE_DATA\|user_mode;	const int ucrw = CPU_PAGE_WRITE_DATA\|user_mode;
UINT32 paddr[2];	UINT32 paddr[2];

paddr[0] = paging(laddr, ucrw);	paddr[0] = paging(laddr, ucrw);
if ((laddr + 1) & 0x00000fff) {	if ((laddr + 1) & PAGE_MASK) {
cpu_memorywrite_w(paddr[0], value);	cpu_memorywrite_w(paddr[0], value);
} else {	} else {
paddr[1] = paging(laddr + 1, ucrw);	paddr[1] = paging(laddr + 1, ucrw);
Line 465 cpu_linear_memory_write_w(UINT32 laddr,	Line 464 cpu_linear_memory_write_w(UINT32 laddr,
void MEMCALL	void MEMCALL
cpu_linear_memory_write_d(UINT32 laddr, UINT32 value, const int user_mode)	cpu_linear_memory_write_d(UINT32 laddr, UINT32 value, const int user_mode)
{	{
const int ucrw = CPU_PAGE_WRITE\|CPU_PAGE_DATA\|user_mode;	const int ucrw = CPU_PAGE_WRITE_DATA\|user_mode;
UINT32 paddr[2];	UINT32 paddr[2];
UINT remain;	UINT remain;

paddr[0] = paging(laddr, ucrw);	paddr[0] = paging(laddr, ucrw);
remain = 0x1000 - (laddr & 0x00000fff);	remain = PAGE_SIZE - (laddr & PAGE_MASK);
if (remain >= 4) {	if (remain >= 4) {
cpu_memorywrite_d(paddr[0], value);	cpu_memorywrite_d(paddr[0], value);
} else {	} else {
Line 499 cpu_linear_memory_write_d(UINT32 laddr,	Line 498 cpu_linear_memory_write_d(UINT32 laddr,
void MEMCALL	void MEMCALL
cpu_linear_memory_write_q(UINT32 laddr, UINT64 value, const int user_mode)	cpu_linear_memory_write_q(UINT32 laddr, UINT64 value, const int user_mode)
{	{
const int ucrw = CPU_PAGE_WRITE\|CPU_PAGE_DATA\|user_mode;	const int ucrw = CPU_PAGE_WRITE_DATA\|user_mode;
UINT32 paddr[2];	UINT32 paddr[2];
UINT remain;	UINT remain;

paddr[0] = paging(laddr, ucrw);	paddr[0] = paging(laddr, ucrw);
remain = 0x1000 - (laddr & 0x00000fff);	remain = PAGE_SIZE - (laddr & PAGE_MASK);
if (remain >= 8) {	if (remain >= 8) {
cpu_memorywrite_q(paddr[0], value);	cpu_memorywrite_q(paddr[0], value);
} else {	} else {
Line 518 cpu_linear_memory_write_q(UINT32 laddr,	Line 517 cpu_linear_memory_write_q(UINT32 laddr,
break;	break;

case 6:	case 6:
	cpu_memorywrite_w(paddr[0], (UINT16)value);
cpu_memorywrite_d(paddr[0] + 2, (UINT32)(value >> 16));	cpu_memorywrite_d(paddr[0] + 2, (UINT32)(value >> 16));
cpu_memorywrite_w(paddr[1], (UINT16)(value >> 48));	cpu_memorywrite_w(paddr[1], (UINT16)(value >> 48));
break;	break;
Line 560 cpu_linear_memory_write_q(UINT32 laddr,	Line 560 cpu_linear_memory_write_q(UINT32 laddr,
void MEMCALL	void MEMCALL
cpu_linear_memory_write_f(UINT32 laddr, const REG80 *value, const int user_mode)	cpu_linear_memory_write_f(UINT32 laddr, const REG80 *value, const int user_mode)
{	{
const int ucrw = CPU_PAGE_WRITE\|CPU_PAGE_DATA\|user_mode;	const int ucrw = CPU_PAGE_WRITE_DATA\|user_mode;
UINT32 paddr[2];	UINT32 paddr[2];
UINT remain;	UINT remain;
UINT i, j;	UINT i, j;

paddr[0] = paging(laddr, ucrw);	paddr[0] = paging(laddr, ucrw);
remain = 0x1000 - (laddr & 0x00000fff);	remain = PAGE_SIZE - (laddr & PAGE_MASK);
if (remain >= 10) {	if (remain >= 10) {
cpu_memorywrite_f(paddr[0], value);	cpu_memorywrite_f(paddr[0], value);
} else {	} else {
Line 582 cpu_linear_memory_write_f(UINT32 laddr,	Line 582 cpu_linear_memory_write_f(UINT32 laddr,


void MEMCALL	void MEMCALL
cpu_memory_access_la_region(UINT32 laddr, UINT length, const int ucrw, BYTE *data)	cpu_memory_access_la_region(UINT32 laddr, UINT length, const int ucrw, UINT8 *data)
{	{
UINT32 paddr;	UINT32 paddr;
UINT remain; /* page remain */	UINT remain; /* page remain */
Line 591 cpu_memory_access_la_region(UINT32 laddr	Line 591 cpu_memory_access_la_region(UINT32 laddr
if (length == 0)	if (length == 0)
return;	return;

remain = 0x1000 - (laddr & 0x00000fff);	remain = PAGE_SIZE - (laddr & PAGE_MASK);
for (;;) {	for (;;) {
if (!CPU_STAT_PAGING) {	if (!CPU_STAT_PAGING) {
paddr = laddr;	paddr = laddr;
Line 615 cpu_memory_access_la_region(UINT32 laddr	Line 615 cpu_memory_access_la_region(UINT32 laddr
remain -= r;	remain -= r;
if (remain <= 0) {	if (remain <= 0) {
/* next page */	/* next page */
remain += 0x1000;	remain += PAGE_SIZE;
}	}
}	}
}	}

void MEMCALL	UINT32 MEMCALL
paging_check(UINT32 laddr, UINT length, const int ucrw)	laddr2paddr(const UINT32 laddr, const int ucrw)
{	{
UINT32 paddr;
UINT remain; /* page remain */
UINT r;

remain = 0x1000 - (laddr & 0x00000fff);
for (;;) {
paddr = paging(laddr, ucrw);

r = (remain > length) ? length : remain;	return paging(laddr, ucrw);

length -= r;
if (length == 0)
break;

laddr += r;
remain -= r;
if (remain <= 0) {
/* next page */
remain += 0x1000;
}
}
}	}

static UINT32 MEMCALL	static UINT32 MEMCALL
Line 656 paging(const UINT32 laddr, const int ucr	Line 637 paging(const UINT32 laddr, const int ucr
UINT32 pte; /* page table entry */	UINT32 pte; /* page table entry */
UINT bit;	UINT bit;
UINT err;	UINT err;
#if defined(IA32_SUPPORT_TLB)
TLB_ENTRY_T *ep;	TLB_ENTRY_T *ep;

ep = tlb_lookup(laddr, ucrw);	ep = tlb_lookup(laddr, ucrw);
if (ep != NULL)	if (ep != NULL)
return ep->paddr + (laddr & 0xfff);	return ep->paddr + (laddr & PAGE_MASK);
#endif

pde_addr = CPU_STAT_PDE_BASE + ((laddr >> 20) & 0xffc);	pde_addr = CPU_STAT_PDE_BASE + ((laddr >> 20) & 0xffc);
pde = cpu_memoryread_d(pde_addr);	pde = cpu_memoryread_d(pde_addr);
Line 693 paging(const UINT32 laddr, const int ucr	Line 672 paging(const UINT32 laddr, const int ucr
}	}

/* make physical address */	/* make physical address */
paddr = (pte & CPU_PTE_BASEADDR_MASK) + (laddr & 0x00000fff);	paddr = (pte & CPU_PTE_BASEADDR_MASK) + (laddr & PAGE_MASK);

bit = ucrw & (CPU_PAGE_WRITE\|CPU_PAGE_USER_MODE);	bit = ucrw & (CPU_PAGE_WRITE\|CPU_PAGE_USER_MODE);
bit \|= (pde & pte & (CPU_PTE_WRITABLE\|CPU_PTE_USER_MODE));	bit \|= (pde & pte & (CPU_PTE_WRITABLE\|CPU_PTE_USER_MODE));
Line 718 paging(const UINT32 laddr, const int ucr	Line 697 paging(const UINT32 laddr, const int ucr
cpu_memorywrite_d(pte_addr, pte);	cpu_memorywrite_d(pte_addr, pte);
}	}

#if defined(IA32_SUPPORT_TLB)
tlb_update(laddr, pte, (bit & (CPU_PTE_WRITABLE\|CPU_PTE_USER_MODE)) + ((ucrw & CPU_PAGE_CODE) >> 1));	tlb_update(laddr, pte, (bit & (CPU_PTE_WRITABLE\|CPU_PTE_USER_MODE)) + ((ucrw & CPU_PAGE_CODE) >> 1));
#endif
return paddr;	return paddr;

pf_exception:	pf_exception:
Line 731 pf_exception:	Line 709 pf_exception:
return 0; /* compiler happy */	return 0; /* compiler happy */
}	}


#if defined(IA32_SUPPORT_TLB)
/*	/*
* TLB	* TLB
*/	*/
Line 758 do { \	Line 734 do { \
#if (CPU_FEATURES & CPU_FEATURE_PGE) == CPU_FEATURE_PGE	#if (CPU_FEATURES & CPU_FEATURE_PGE) == CPU_FEATURE_PGE
#define TLB_IS_GLOBAL(ep) ((ep)->tag & TLB_ENTRY_TAG_GLOBAL)	#define TLB_IS_GLOBAL(ep) ((ep)->tag & TLB_ENTRY_TAG_GLOBAL)
#else	#else
#define TLB_IS_GLOBAL(ep) FALSE	#define TLB_IS_GLOBAL(ep) 0
#endif	#endif

#define TLB_SET_TAG_FLAGS(ep, entry, bit) \	#define TLB_SET_TAG_FLAGS(ep, entry, bit) \
Line 804 tlb_init(void)	Line 780 tlb_init(void)

memset(tlb, 0, sizeof(tlb));	memset(tlb, 0, sizeof(tlb));
#if defined(IA32_PROFILE_TLB)	#if defined(IA32_PROFILE_TLB)
memset(tlb_profile, 0, sizeof(tlb_profile));	memset(&tlb_profile, 0, sizeof(tlb_profile));
#endif /* IA32_PROFILE_TLB */	#endif /* IA32_PROFILE_TLB */
}	}

Line 921 tlb_update(const UINT32 laddr, const UIN	Line 897 tlb_update(const UINT32 laddr, const UIN
}	}
ep->memp = NULL;	ep->memp = NULL;
}	}
#endif /* IA32_SUPPORT_TLB */

RetroPC.NET-CVS <cvs@retropc.net>

Removed from v.1.29
changed lines
	Added in v.1.34