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| version 1.4, 2004/01/23 14:33:26 | version 1.6, 2004/01/26 15:22:16 |
|---|---|
| Line 214 cpu_linear_memory_read(DWORD laddr, DWOR | Line 214 cpu_linear_memory_read(DWORD laddr, DWOR |
| r = (remain > length) ? length : remain; | r = (remain > length) ? length : remain; |
| switch (r) { | switch (r) { |
| case 1: | case 1: |
| value = (DWORD)cpu_memoryread(paddr) << shift; | value |= (DWORD)cpu_memoryread(paddr) << shift; |
| shift += 8; | shift += 8; |
| break; | break; |
| Line 225 cpu_linear_memory_read(DWORD laddr, DWOR | Line 225 cpu_linear_memory_read(DWORD laddr, DWOR |
| case 3: | case 3: |
| value |= (DWORD)cpu_memoryread_w(paddr) << shift; | value |= (DWORD)cpu_memoryread_w(paddr) << shift; |
| value |= (DWORD)cpu_memoryread(paddr + 2) << (shift+16); | shift += 16; |
| shift += 24; | value |= (DWORD)cpu_memoryread(paddr + 2) << shift; |
| shift += 8; | |
| break; | break; |
| case 4: | case 4: |
| value = cpu_memoryread_d(paddr); | value = cpu_memoryread_d(paddr); |
| shift += 32; | |
| break; | break; |
| default: | default: |
| Line 273 cpu_linear_memory_write(DWORD laddr, DWO | Line 273 cpu_linear_memory_write(DWORD laddr, DWO |
| r = (remain > length) ? length : remain; | r = (remain > length) ? length : remain; |
| switch (r) { | switch (r) { |
| case 1: | case 1: |
| cpu_memorywrite(paddr, value); | cpu_memorywrite(paddr, value & 0xff); |
| value >>= 8; | value >>= 8; |
| break; | break; |
| case 2: | case 2: |
| cpu_memorywrite_w(paddr, value); | cpu_memorywrite_w(paddr, value & 0xffff); |
| value >>= 16; | value >>= 16; |
| break; | break; |
| case 3: | case 3: |
| cpu_memorywrite_w(paddr, value); | cpu_memorywrite_w(paddr, value & 0xffff); |
| cpu_memorywrite(paddr, value >> 16); | value >>= 16; |
| value >>= 24; | cpu_memorywrite(paddr + 2, value & 0xff); |
| value >>= 8; | |
| break; | break; |
| case 4: | case 4: |
| Line 346 paging(DWORD laddr, int crw, int user_mo | Line 347 paging(DWORD laddr, int crw, int user_mo |
| DWORD pte_addr; /* page table entry address */ | DWORD pte_addr; /* page table entry address */ |
| DWORD pte; /* page table entry */ | DWORD pte; /* page table entry */ |
| DWORD bit; | DWORD bit; |
| DWORD err = 0; | DWORD err; |
| #if defined(IA32_SUPPORT_TLB) | #if defined(IA32_SUPPORT_TLB) |
| if (tlb_lookup(laddr, crw, &paddr)) | if (tlb_lookup(laddr, crw, &paddr)) |