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| version 1.8, 2004/02/03 14:27:07 | version 1.9, 2004/02/03 14:49:39 |
|---|---|
| Line 213 cpu_linear_memory_read(DWORD laddr, DWOR | Line 213 cpu_linear_memory_read(DWORD laddr, DWOR |
| r = (remain > length) ? length : remain; | r = (remain > length) ? length : remain; |
| switch (r) { | switch (r) { |
| case 1: | case 4: |
| value |= (DWORD)cpu_memoryread(paddr) << shift; | value = cpu_memoryread_d(paddr); |
| shift += 8; | |
| break; | break; |
| case 3: | |
| value |= (DWORD)cpu_memoryread(paddr) << shift; | |
| shift += 8; | |
| paddr++; | |
| /*FALLTHROUGH*/ | |
| case 2: | case 2: |
| value |= (DWORD)cpu_memoryread_w(paddr) << shift; | value |= (DWORD)cpu_memoryread_w(paddr) << shift; |
| shift += 16; | shift += 16; |
| break; | break; |
| case 3: | case 1: |
| value |= (DWORD)cpu_memoryread_w(paddr) << shift; | value |= (DWORD)cpu_memoryread(paddr) << shift; |
| shift += 16; | |
| value |= (DWORD)cpu_memoryread(paddr + 2) << shift; | |
| shift += 8; | shift += 8; |
| break; | break; |
| case 4: | |
| value = cpu_memoryread_d(paddr); | |
| break; | |
| default: | default: |
| ia32_panic("cpu_linear_memory_read(): out of range (r = %d)\n", r); | ia32_panic("cpu_linear_memory_read(): out of range (r = %d)\n", r); |
| break; | break; |
| Line 255 cpu_linear_memory_read(DWORD laddr, DWOR | Line 253 cpu_linear_memory_read(DWORD laddr, DWOR |
| } | } |
| void MEMCALL | void MEMCALL |
| cpu_linear_memory_write(DWORD laddr, DWORD length, DWORD value) | cpu_linear_memory_write(DWORD laddr, DWORD value, DWORD length) |
| { | { |
| DWORD paddr; | DWORD paddr; |
| DWORD remain; /* page remain */ | DWORD remain; /* page remain */ |
| Line 274 cpu_linear_memory_write(DWORD laddr, DWO | Line 272 cpu_linear_memory_write(DWORD laddr, DWO |
| r = (remain > length) ? length : remain; | r = (remain > length) ? length : remain; |
| switch (r) { | switch (r) { |
| case 1: | case 4: |
| cpu_memorywrite(paddr, value & 0xff); | cpu_memorywrite_d(paddr, value); |
| value >>= 8; | |
| break; | break; |
| case 3: | |
| cpu_memorywrite(paddr, value & 0xff); | |
| value >>= 8; | |
| paddr++; | |
| /*FALLTHROUGH*/ | |
| case 2: | case 2: |
| cpu_memorywrite_w(paddr, value & 0xffff); | cpu_memorywrite_w(paddr, value & 0xffff); |
| value >>= 16; | value >>= 16; |
| break; | break; |
| case 3: | case 1: |
| cpu_memorywrite_w(paddr, value & 0xffff); | cpu_memorywrite(paddr, value & 0xff); |
| value >>= 16; | |
| cpu_memorywrite(paddr + 2, value & 0xff); | |
| value >>= 8; | value >>= 8; |
| break; | break; |
| case 4: | |
| cpu_memorywrite_d(paddr, value); | |
| break; | |
| default: | default: |
| ia32_panic("cpu_linear_memory_write(): out of range (r = %d)\n", r); | ia32_panic("cpu_linear_memory_write(): out of range (r = %d)\n", r); |
| break; | break; |
| Line 361 paging(DWORD laddr, int crw, int user_mo | Line 357 paging(DWORD laddr, int crw, int user_mo |
| return paddr; | return paddr; |
| #endif /* IA32_SUPPORT_TLB */ | #endif /* IA32_SUPPORT_TLB */ |
| pde_addr = (CPU_CR3 & CPU_CR3_PD_MASK) | ((laddr >> 20) & 0xffc); | pde_addr = CPU_STAT_PDE_BASE | ((laddr >> 20) & 0xffc); |
| pde = cpu_memoryread_d(pde_addr); | pde = cpu_memoryread_d(pde_addr); |
| if (!(pde & CPU_PDE_PRESENT)) { | if (!(pde & CPU_PDE_PRESENT)) { |
| VERBOSE(("paging: PDE is not present")); | VERBOSE(("paging: PDE is not present")); |