--- np2/i386c/ia32/paging.c	2004/03/05 14:17:35	1.13
+++ np2/i386c/ia32/paging.c	2005/03/12 12:32:54	1.28
@@ -1,7 +1,7 @@
-/*	$Id: paging.c,v 1.13 2004/03/05 14:17:35 monaka Exp $	*/
+/*	$Id: paging.c,v 1.28 2005/03/12 12:32:54 monaka Exp $	*/
 
 /*
- * Copyright (c) 2003 NONAKA Kimihiro
+ * Copyright (c) 2003-2004 NONAKA Kimihiro
  * All rights reserved.
  *
  * Redistribution and use in source and binary forms, with or without
@@ -12,8 +12,6 @@
  * 2. Redistributions in binary form must reproduce the above copyright
  *    notice, this list of conditions and the following disclaimer in the
  *    documentation and/or other materials provided with the distribution.
- * 3. The name of the author may not be used to endorse or promote products
- *    derived from this software without specific prior written permission.
  *
  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
@@ -184,148 +182,435 @@ static const UINT8 page_access_bit[32] =
  * +- CR3(物理アドレス)
  */
 
-static UINT32 paging(UINT32 laddr, int crw, int user_mode);
+static UINT32 MEMCALL paging(const UINT32 laddr, const int ucrw) GCC_ATTR_REGPARM;
 #if defined(IA32_SUPPORT_TLB)
-static BOOL tlb_lookup(UINT32 vaddr, int crw, UINT32 *paddr);
-static void tlb_update(UINT32 laddr, UINT entry, int crw);
+static void MEMCALL tlb_update(const UINT32 laddr, const UINT entry, const int ucrw) GCC_ATTR_REGPARM;
 #endif
 
-
-void
-cpu_memory_access_la_region(UINT32 laddr, UINT length, int crw, int user_mode, BYTE *data)
+UINT8 MEMCALL
+cpu_memory_access_la_RMW_b(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg)
 {
+	const int ucrw = CPU_PAGE_WRITE|CPU_PAGE_DATA|CPU_STAT_USER_MODE;
+	UINT32 result, value;
 	UINT32 paddr;
-	UINT remain;	/* page remain */
-	UINT r;
 
-	if (length == 0)
-		return;
+	paddr = paging(laddr, ucrw);
+	value = cpu_memoryread(paddr);
+	result = (*func)(value, arg);
+	cpu_memorywrite(paddr, (UINT8)result);
+
+	return value;
+}
+
+UINT16 MEMCALL
+cpu_memory_access_la_RMW_w(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg)
+{
+	const int ucrw = CPU_PAGE_WRITE|CPU_PAGE_DATA|CPU_STAT_USER_MODE;
+	UINT32 result, value;
+	UINT32 paddr[2];
+
+	paddr[0] = paging(laddr, ucrw);
+	if ((laddr + 1) & 0x00000fff) {
+		value = cpu_memoryread_w(paddr[0]);
+		result = (*func)(value, arg);
+		cpu_memorywrite_w(paddr[0], (UINT16)result);
+	} else {
+		paddr[1] = paging(laddr + 1, ucrw);
+		value = cpu_memoryread_b(paddr[0]);
+		value += (UINT16)cpu_memoryread_b(paddr[1]) << 8;
+		result = (*func)(value, arg);
+		cpu_memorywrite(paddr[0], (UINT8)result);
+		cpu_memorywrite(paddr[1], (UINT8)(result >> 8));
+	}
+	return value;
+}
 
+UINT32 MEMCALL
+cpu_memory_access_la_RMW_d(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg)
+{
+	const int ucrw = CPU_PAGE_WRITE|CPU_PAGE_DATA|CPU_STAT_USER_MODE;
+	UINT32 result, value;
+	UINT32 paddr[2];
+	UINT remain;
+
+	paddr[0] = paging(laddr, ucrw);
 	remain = 0x1000 - (laddr & 0x00000fff);
-	for (;;) {
-		if (!CPU_STAT_PAGING) {
-			paddr = laddr;
-		} else {
-			paddr = paging(laddr, crw, user_mode);
-		}
+	if (remain >= 4) {
+		value = cpu_memoryread_d(paddr[0]);
+		result = (*func)(value, arg);
+		cpu_memorywrite_d(paddr[0], result);
+	} else {
+		paddr[1] = paging(laddr + remain, ucrw);
+		switch (remain) {
+		case 3:
+			value = cpu_memoryread(paddr[0]);
+			value += (UINT32)cpu_memoryread_w(paddr[0] + 1) << 8;
+			value += (UINT32)cpu_memoryread(paddr[1]) << 24;
+			result = (*func)(value, arg);
+			cpu_memorywrite(paddr[0], (UINT8)result);
+			cpu_memorywrite_w(paddr[0] + 1, (UINT16)(result >> 8));
+			cpu_memorywrite(paddr[1], (UINT8)(result >> 24));
+			break;
 
-		r = (remain > length) ? length : remain;
-		if (!(crw & CPU_PAGE_WRITE)) {
-			cpu_memoryread_region(paddr, data, r);
-		} else {
-			cpu_memorywrite_region(paddr, data, r);
-		}
+		case 2:
+			value = cpu_memoryread_w(paddr[0]);
+			value += (UINT32)cpu_memoryread_w(paddr[1]) << 16;
+			result = (*func)(value, arg);
+			cpu_memorywrite_w(paddr[0], (UINT16)result);
+			cpu_memorywrite_w(paddr[1], (UINT16)(result >> 16));
+			break;
 
-		length -= r;
-		if (length == 0)
+		case 1:
+			value = cpu_memoryread(paddr[0]);
+			value += (UINT32)cpu_memoryread_w(paddr[1]) << 8;
+			value += (UINT32)cpu_memoryread(paddr[1] + 2) << 24;
+			result = (*func)(value, arg);
+			cpu_memorywrite(paddr[0], (UINT8)result);
+			cpu_memorywrite_w(paddr[1], (UINT16)(result >> 8));
+			cpu_memorywrite(paddr[1] + 2, (UINT8)(result >> 24));
 			break;
 
-		data += r;
-		laddr += r;
-		remain -= r;
-		if (remain <= 0) {
-			/* next page */
-			remain += 0x1000;
+		default:
+			ia32_panic("cpu_memory_access_la_RMW_d(): out of range (remain = %d)\n", remain);
+			return (UINT32)-1;
 		}
 	}
+	return value;
 }
 
-UINT32 MEMCALL
-cpu_linear_memory_read(UINT32 laddr, UINT length, int crw, int user_mode)
+UINT8 MEMCALL
+cpu_linear_memory_read_b(UINT32 laddr, const int ucrw)
 {
-	UINT32 value = 0;
 	UINT32 paddr;
-	UINT remain;	/* page remain */
-	UINT r;
-	int shift = 0;
 
+	paddr = paging(laddr, ucrw);
+	return cpu_memoryread(paddr);
+}
+
+UINT16 MEMCALL
+cpu_linear_memory_read_w(UINT32 laddr, const int ucrw)
+{
+	UINT32 paddr[2];
+	UINT16 value;
+
+	paddr[0] = paging(laddr, ucrw);
+	if ((laddr + 1) & 0x00000fff) {
+		return cpu_memoryread_w(paddr[0]);
+	} else {
+		paddr[1] = paging(laddr + 1, ucrw);
+		value = cpu_memoryread_b(paddr[0]);
+		value += (UINT16)cpu_memoryread_b(paddr[1]) << 8;
+		return value;
+	}
+}
+
+UINT32 MEMCALL
+cpu_linear_memory_read_d(UINT32 laddr, const int ucrw)
+{
+	UINT32 paddr[2];
+	UINT32 value;
+	UINT remain;
+
+	paddr[0] = paging(laddr, ucrw);
 	remain = 0x1000 - (laddr & 0x00000fff);
-	for (;;) {
-		paddr = paging(laddr, crw, user_mode);
+	if (remain >= 4) {
+		return cpu_memoryread_d(paddr[0]);
+	} else {
+		paddr[1] = paging(laddr + remain, ucrw);
+		switch (remain) {
+		case 3:
+			value = cpu_memoryread(paddr[0]);
+			value += (UINT32)cpu_memoryread_w(paddr[0] + 1) << 8;
+			value += (UINT32)cpu_memoryread(paddr[1]) << 24;
+			break;
+
+		case 2:
+			value = cpu_memoryread_w(paddr[0]);
+			value += (UINT32)cpu_memoryread_w(paddr[1]) << 16;
+			break;
+
+		case 1:
+			value = cpu_memoryread(paddr[0]);
+			value += (UINT32)cpu_memoryread_w(paddr[1]) << 8;
+			value += (UINT32)cpu_memoryread(paddr[1] + 2) << 24;
+			break;
+
+		default:
+			ia32_panic("cpu_linear_memory_read_d(): out of range (remain = %d)\n", remain);
+			value = (UINT32)-1;
+			break;
+		}
+		return value;
+	}
+}
+
+UINT64 MEMCALL
+cpu_linear_memory_read_q(UINT32 laddr, const int ucrw)
+{
+	UINT32 paddr[2];
+	UINT64 value;
+	UINT remain;
+
+	paddr[0] = paging(laddr, ucrw);
+	remain = 0x1000 - (laddr & 0x00000fff);
+	if (remain >= 8) {
+		return cpu_memoryread_q(paddr[0]);
+	} else {
+		paddr[1] = paging(laddr + remain, ucrw);
+		switch (remain) {
+		case 7:
+			value = cpu_memoryread(paddr[0]);
+			value += (UINT64)cpu_memoryread_w(paddr[0] + 1) << 8;
+			value += (UINT64)cpu_memoryread_d(paddr[0] + 3) << 24;
+			value += (UINT64)cpu_memoryread(paddr[1]) << 56;
+			break;
+
+		case 6:
+			value = cpu_memoryread_w(paddr[0]);
+			value += (UINT64)cpu_memoryread_d(paddr[0] + 2) << 16;
+			value += (UINT64)cpu_memoryread_w(paddr[1]) << 48;
+			break;
+
+		case 5:
+			value = cpu_memoryread(paddr[0]);
+			value += (UINT64)cpu_memoryread_d(paddr[0] + 1) << 8;
+			value += (UINT64)cpu_memoryread_w(paddr[1]) << 40;
+			value += (UINT64)cpu_memoryread(paddr[1] + 1) << 56;
+			break;
 
-		r = (remain > length) ? length : remain;
-		switch (r) {
 		case 4:
-			value = cpu_memoryread_d(paddr);
+			value = cpu_memoryread_d(paddr[0]);
+			value += (UINT64)cpu_memoryread_d(paddr[1]) << 32;
 			break;
 
 		case 3:
-			value += (UINT32)cpu_memoryread(paddr) << shift;
-			shift += 8;
-			paddr++;
-			/*FALLTHROUGH*/
+			value = cpu_memoryread(paddr[0]);
+			value += (UINT64)cpu_memoryread_w(paddr[0] + 1) << 8;
+			value += (UINT64)cpu_memoryread_d(paddr[1]) << 24;
+			value += (UINT64)cpu_memoryread(paddr[1] + 4) << 56;
+			break;
+
 		case 2:
-			value += (UINT32)cpu_memoryread_w(paddr) << shift;
-			shift += 16;
+			value = cpu_memoryread_w(paddr[0]);
+			value += (UINT64)cpu_memoryread_d(paddr[1]) << 16;
+			value += (UINT64)cpu_memoryread_w(paddr[1] + 4) << 48;
 			break;
 
 		case 1:
-			value += (UINT32)cpu_memoryread(paddr) << shift;
-			shift += 8;
+			value = cpu_memoryread(paddr[0]);
+			value += (UINT64)cpu_memoryread_d(paddr[1]) << 8;
+			value += (UINT64)cpu_memoryread_w(paddr[1] + 4) << 40;
+			value += (UINT64)cpu_memoryread(paddr[1] + 6) << 56;
 			break;
 
 		default:
-			ia32_panic("cpu_linear_memory_read(): out of range (r = %d)\n", r);
+			ia32_panic("cpu_linear_memory_read_q(): out of range (remain = %d)\n", remain);
+			value = (UINT64)-1;
 			break;
 		}
+	}
+	return value;
+}
 
-		length -= r;
-		if (length == 0)
-			break;
+REG80 MEMCALL
+cpu_linear_memory_read_f(UINT32 laddr, const int ucrw)
+{
+	UINT32 paddr[2];
+	REG80 value;
+	UINT remain;
+	UINT i, j;
 
-		laddr += r;
-		remain -= r;
-		if (remain <= 0) {
-			/* next page */
-			remain += 0x1000;
+	paddr[0] = paging(laddr, ucrw);
+	remain = 0x1000 - (laddr & 0x00000fff);
+	if (remain >= 10) {
+		return cpu_memoryread_f(paddr[0]);
+	} else {
+		paddr[1] = paging(laddr + remain, ucrw);
+		for (i = 0; i < remain; ++i) {
+			value.b[i] = cpu_memoryread(paddr[0] + i);
+		}
+		for (j = 0; i < 10; ++i, ++j) {
+			value.b[i] = cpu_memoryread(paddr[1] + j);
 		}
+		return value;
 	}
-
-	return value;
 }
 
 void MEMCALL
-cpu_linear_memory_write(UINT32 laddr, UINT32 value, UINT length, int user_mode)
+cpu_linear_memory_write_b(UINT32 laddr, UINT8 value, const int user_mode)
 {
+	const int ucrw = CPU_PAGE_WRITE|CPU_PAGE_DATA|user_mode;
 	UINT32 paddr;
-	UINT remain;	/* page remain */
-	UINT r;
-	int crw = (CPU_PAGE_WRITE|CPU_PAGE_DATA);
 
+	paddr = paging(laddr, ucrw);
+	cpu_memorywrite(paddr, value);
+}
+
+void MEMCALL
+cpu_linear_memory_write_w(UINT32 laddr, UINT16 value, const int user_mode)
+{
+	const int ucrw = CPU_PAGE_WRITE|CPU_PAGE_DATA|user_mode;
+	UINT32 paddr[2];
+
+	paddr[0] = paging(laddr, ucrw);
+	if ((laddr + 1) & 0x00000fff) {
+		cpu_memorywrite_w(paddr[0], value);
+	} else {
+		paddr[1] = paging(laddr + 1, ucrw);
+		cpu_memorywrite(paddr[0], (UINT8)value);
+		cpu_memorywrite(paddr[1], (UINT8)(value >> 8));
+	}
+}
+
+void MEMCALL
+cpu_linear_memory_write_d(UINT32 laddr, UINT32 value, const int user_mode)
+{
+	const int ucrw = CPU_PAGE_WRITE|CPU_PAGE_DATA|user_mode;
+	UINT32 paddr[2];
+	UINT remain;
+
+	paddr[0] = paging(laddr, ucrw);
 	remain = 0x1000 - (laddr & 0x00000fff);
-	for (;;) {
-		paddr = paging(laddr, crw, user_mode);
+	if (remain >= 4) {
+		cpu_memorywrite_d(paddr[0], value);
+	} else {
+		paddr[1] = paging(laddr + remain, ucrw);
+		switch (remain) {
+		case 3:
+			cpu_memorywrite(paddr[0], (UINT8)value);
+			cpu_memorywrite_w(paddr[0] + 1, (UINT16)(value >> 8));
+			cpu_memorywrite(paddr[1], (UINT8)(value >> 24));
+			break;
+
+		case 2:
+			cpu_memorywrite_w(paddr[0], (UINT16)value);
+			cpu_memorywrite_w(paddr[1], (UINT16)(value >> 16));
+			break;
+
+		case 1:
+			cpu_memorywrite(paddr[0], (UINT8)value);
+			cpu_memorywrite_w(paddr[1], (UINT16)(value >> 8));
+			cpu_memorywrite(paddr[1] + 2, (UINT8)(value >> 24));
+			break;
+		}
+	}
+}
+
+void MEMCALL
+cpu_linear_memory_write_q(UINT32 laddr, UINT64 value, const int user_mode)
+{
+	const int ucrw = CPU_PAGE_WRITE|CPU_PAGE_DATA|user_mode;
+	UINT32 paddr[2];
+	UINT remain;
+
+	paddr[0] = paging(laddr, ucrw);
+	remain = 0x1000 - (laddr & 0x00000fff);
+	if (remain >= 8) {
+		cpu_memorywrite_q(paddr[0], value);
+	} else {
+		paddr[1] = paging(laddr + remain, ucrw);
+		switch (remain) {
+		case 7:
+			cpu_memorywrite(paddr[0], (UINT8)value);
+			cpu_memorywrite_w(paddr[0] + 1, (UINT16)(value >> 8));
+			cpu_memorywrite_d(paddr[0] + 3, (UINT32)(value >> 24));
+			cpu_memorywrite(paddr[1], (UINT8)(value >> 56));
+			break;
+
+		case 6:
+			cpu_memorywrite_d(paddr[0] + 2, (UINT32)(value >> 16));
+			cpu_memorywrite_w(paddr[1], (UINT16)(value >> 48));
+			break;
+
+		case 5:
+			cpu_memorywrite(paddr[0], (UINT8)value);
+			cpu_memorywrite_d(paddr[0] + 1, (UINT32)(value >> 8));
+			cpu_memorywrite_w(paddr[1], (UINT16)(value >> 40));
+			cpu_memorywrite(paddr[1] + 2, (UINT8)(value >> 56));
+			break;
 
-		r = (remain > length) ? length : remain;
-		switch (r) {
 		case 4:
-			cpu_memorywrite_d(paddr, value);
+			cpu_memorywrite_d(paddr[0], (UINT32)value);
+			cpu_memorywrite_d(paddr[1], (UINT32)(value >> 32));
 			break;
 
 		case 3:
-			cpu_memorywrite(paddr, value & 0xff);
-			value >>= 8;
-			paddr++;
-			/*FALLTHROUGH*/
+			cpu_memorywrite(paddr[0], (UINT8)value);
+			cpu_memorywrite_w(paddr[0] + 1, (UINT16)(value >> 8));
+			cpu_memorywrite_d(paddr[1], (UINT32)(value >> 24));
+			cpu_memorywrite(paddr[1] + 4, (UINT8)(value >> 56));
+			break;
+
 		case 2:
-			cpu_memorywrite_w(paddr, value & 0xffff);
-			value >>= 16;
+			cpu_memorywrite_w(paddr[0], (UINT16)value);
+			cpu_memorywrite_d(paddr[1], (UINT32)(value >> 16));
+			cpu_memorywrite_w(paddr[1] + 4, (UINT16)(value >> 48));
 			break;
 
 		case 1:
-			cpu_memorywrite(paddr, value & 0xff);
-			value >>= 8;
+			cpu_memorywrite(paddr[0], (UINT8)value);
+			cpu_memorywrite_d(paddr[1], (UINT32)(value >> 8));
+			cpu_memorywrite_w(paddr[1] + 4, (UINT16)(value >> 40));
+			cpu_memorywrite(paddr[1] + 6, (UINT8)(value >> 56));
 			break;
+		}
+	}
+}
 
-		default:
-			ia32_panic("cpu_linear_memory_write(): out of range (r = %d)\n", r);
-			break;
+void MEMCALL
+cpu_linear_memory_write_f(UINT32 laddr, const REG80 *value, const int user_mode)
+{
+	const int ucrw = CPU_PAGE_WRITE|CPU_PAGE_DATA|user_mode;
+	UINT32 paddr[2];
+	UINT remain;
+	UINT i, j;
+
+	paddr[0] = paging(laddr, ucrw);
+	remain = 0x1000 - (laddr & 0x00000fff);
+	if (remain >= 10) {
+		cpu_memorywrite_f(paddr[0], value);
+	} else {
+		paddr[1] = paging(laddr + remain, ucrw);
+		for (i = 0; i < remain; ++i) {
+			cpu_memorywrite(paddr[0] + i, value->b[i]);
+		}
+		for (j = 0; i < 10; ++i, ++j) {
+			cpu_memorywrite(paddr[1] + j, value->b[i]);
+		}
+	}
+}
+
+
+void MEMCALL
+cpu_memory_access_la_region(UINT32 laddr, UINT length, const int ucrw, BYTE *data)
+{
+	UINT32 paddr;
+	UINT remain;	/* page remain */
+	UINT r;
+
+	if (length == 0)
+		return;
+
+	remain = 0x1000 - (laddr & 0x00000fff);
+	for (;;) {
+		if (!CPU_STAT_PAGING) {
+			paddr = laddr;
+		} else {
+			paddr = paging(laddr, ucrw);
+		}
+
+		r = (remain > length) ? length : remain;
+		if (!(ucrw & CPU_PAGE_WRITE)) {
+			cpu_memoryread_region(paddr, data, r);
+		} else {
+			cpu_memorywrite_region(paddr, data, r);
 		}
 
 		length -= r;
 		if (length == 0)
 			break;
 
+		data += r;
 		laddr += r;
 		remain -= r;
 		if (remain <= 0) {
@@ -336,7 +621,7 @@ cpu_linear_memory_write(UINT32 laddr, UI
 }
 
 void MEMCALL
-paging_check(UINT32 laddr, UINT length, int crw, int user_mode)
+paging_check(UINT32 laddr, UINT length, const int ucrw)
 {
 	UINT32 paddr;
 	UINT remain;	/* page remain */
@@ -344,7 +629,7 @@ paging_check(UINT32 laddr, UINT length, 
 
 	remain = 0x1000 - (laddr & 0x00000fff);
 	for (;;) {
-		paddr = paging(laddr, crw, user_mode);
+		paddr = paging(laddr, ucrw);
 
 		r = (remain > length) ? length : remain;
 
@@ -361,8 +646,8 @@ paging_check(UINT32 laddr, UINT length, 
 	}
 }
 
-static UINT32
-paging(UINT32 laddr, int crw, int user_mode)
+static UINT32 MEMCALL
+paging(const UINT32 laddr, const int ucrw)
 {
 	UINT32 paddr;		/* physical address */
 	UINT32 pde_addr;	/* page directory entry address */
@@ -371,11 +656,13 @@ paging(UINT32 laddr, int crw, int user_m
 	UINT32 pte;		/* page table entry */
 	UINT bit;
 	UINT err;
-
 #if defined(IA32_SUPPORT_TLB)
-	if (tlb_lookup(laddr, crw, &paddr))
-		return paddr;
-#endif	/* IA32_SUPPORT_TLB */
+	TLB_ENTRY_T *ep;
+
+	ep = tlb_lookup(laddr, ucrw);
+	if (ep != NULL)
+		return ep->paddr + (laddr & 0xfff);
+#endif
 
 	pde_addr = CPU_STAT_PDE_BASE + ((laddr >> 20) & 0xffc);
 	pde = cpu_memoryread_d(pde_addr);
@@ -408,9 +695,8 @@ paging(UINT32 laddr, int crw, int user_m
 	/* make physical address */
 	paddr = (pte & CPU_PTE_BASEADDR_MASK) + (laddr & 0x00000fff);
 
-	bit  = crw & CPU_PAGE_WRITE;
+	bit  = ucrw & (CPU_PAGE_WRITE|CPU_PAGE_USER_MODE);
 	bit |= (pde & pte & (CPU_PTE_WRITABLE|CPU_PTE_USER_MODE));
-	bit |= (user_mode << 3);
 	bit |= CPU_STAT_WP;
 
 #if !defined(USE_PAGE_ACCESS_TABLE)
@@ -427,28 +713,70 @@ paging(UINT32 laddr, int crw, int user_m
 		goto pf_exception;
 	}
 
-	if ((crw & CPU_PAGE_WRITE) && !(pte & CPU_PTE_DIRTY)) {
+	if ((ucrw & CPU_PAGE_WRITE) && !(pte & CPU_PTE_DIRTY)) {
 		pte |= CPU_PTE_DIRTY;
 		cpu_memorywrite_d(pte_addr, pte);
 	}
 
 #if defined(IA32_SUPPORT_TLB)
-	tlb_update(laddr, pte, crw);
-#endif	/* IA32_SUPPORT_TLB */
-
+	tlb_update(laddr, pte, (bit & (CPU_PTE_WRITABLE|CPU_PTE_USER_MODE)) + ((ucrw & CPU_PAGE_CODE) >> 1));
+#endif
 	return paddr;
 
 pf_exception:
 	CPU_CR2 = laddr;
-	err |= ((crw & CPU_PAGE_WRITE) << 1) | (user_mode << 2);
+	err |= (ucrw & CPU_PAGE_WRITE) << 1;
+	err |= (ucrw & CPU_PAGE_USER_MODE) >> 1;
 	EXCEPTION(PF_EXCEPTION, err);
 	return 0;	/* compiler happy */
 }
 
+
 #if defined(IA32_SUPPORT_TLB)
 /* 
  * TLB
  */
+#define	TLB_GET_PADDR(ep, addr)	((ep)->paddr + ((addr) & ~CPU_PTE_BASEADDR_MASK))
+#define	TLB_SET_PADDR(ep, addr)	((ep)->paddr = (addr) & CPU_PTE_BASEADDR_MASK)
+
+#define	TLB_TAG_SHIFT		TLB_ENTRY_TAG_MAX_SHIFT
+#define	TLB_TAG_MASK		(~((1 << TLB_TAG_SHIFT) - 1))
+#define	TLB_GET_TAG_ADDR(ep)	((ep)->tag & TLB_TAG_MASK)
+#define	TLB_SET_TAG_ADDR(ep, addr) \
+do { \
+	(ep)->tag &= ~TLB_TAG_MASK; \
+	(ep)->tag |= (addr) & TLB_TAG_MASK; \
+} while (/*CONSTCOND(*/ 0)
+
+#define	TLB_IS_VALID(ep)	((ep)->tag & TLB_ENTRY_TAG_VALID)
+#define	TLB_SET_VALID(ep)	((ep)->tag = TLB_ENTRY_TAG_VALID)
+#define	TLB_SET_INVALID(ep)	((ep)->tag = 0)
+
+#define	TLB_IS_WRITABLE(ep)	((ep)->tag & CPU_PTE_WRITABLE)
+#define	TLB_IS_USERMODE(ep)	((ep)->tag & CPU_PTE_USER_MODE)
+#define	TLB_IS_DIRTY(ep)	((ep)->tag & TLB_ENTRY_TAG_DIRTY)
+#if (CPU_FEATURES & CPU_FEATURE_PGE) == CPU_FEATURE_PGE
+#define	TLB_IS_GLOBAL(ep)	((ep)->tag & TLB_ENTRY_TAG_GLOBAL)
+#else
+#define	TLB_IS_GLOBAL(ep)	FALSE
+#endif
+
+#define	TLB_SET_TAG_FLAGS(ep, entry, bit) \
+do { \
+	(ep)->tag |= (entry) & (CPU_PTE_GLOBAL_PAGE|CPU_PTE_DIRTY); \
+	(ep)->tag |= (bit) & (CPU_PTE_WRITABLE|CPU_PTE_USER_MODE); \
+} while (/*CONSTCOND*/ 0)
+
+#define	NTLB		2	/* 0: DTLB, 1: ITLB */
+#define	NENTRY		(1 << 6)
+#define	TLB_ENTRY_SHIFT	12
+#define	TLB_ENTRY_MASK	(NENTRY - 1)
+
+typedef struct {
+	TLB_ENTRY_T	entry[NENTRY];
+} TLB_T;
+
+static TLB_T tlb[NTLB];
 
 #if defined(IA32_PROFILE_TLB)
 /* profiling */
@@ -470,69 +798,22 @@ static TLB_PROFILE_T tlb_profile;
 #endif	/* IA32_PROFILE_TLB */
 
 
-typedef struct {
-	UINT32	tag;	/* linear address */
-#define	TLB_ENTRY_VALID		(1 << 0)
-#define	TLB_ENTRY_GLOBAL	CPU_PTE_GLOBAL_PAGE
-
-	UINT32	paddr;	/* physical address */
-} TLB_ENTRY_T;
-
-#define	TLB_GET_PADDR(ep, addr)	((ep)->paddr + ((addr) & ~CPU_PTE_BASEADDR_MASK))
-#define	TLB_SET_PADDR(ep, addr)	((ep)->paddr = (addr) & CPU_PTE_BASEADDR_MASK)
-
-#define	TLB_TAG_SHIFT	17
-#define	TLB_TAG_MASK	~((1 << TLB_TAG_SHIFT) - 1)
-#define	TLB_GET_TAG_ADDR(ep)	((ep)->tag & TLB_TAG_MASK)
-#define	TLB_SET_TAG_ADDR(ep, addr) \
-	((ep)->tag = ((addr) & TLB_TAG_MASK) + ((ep)->tag & ~TLB_TAG_MASK))
-
-#define	TLB_IS_VALID(ep)	((ep)->tag & TLB_ENTRY_VALID)
-#define	TLB_SET_VALID(ep)	((ep)->tag |= TLB_ENTRY_VALID)
-#define	TLB_CLEAR_VALID(ep)	((ep)->tag &= ~TLB_ENTRY_VALID)
-
-#if CPU_FAMILY == 4
-#define	TLB_IS_GLOBAL(ep)	FALSE
-#define	TLB_SET_GLOBAL(ep)	(void)(ep)
-#define	TLB_CLEAR_GLOBAL(ep)	(void)(ep)
-#else
-#define	TLB_IS_GLOBAL(ep)	((ep)->tag & TLB_ENTRY_GLOBAL)
-#define	TLB_SET_GLOBAL(ep)	((ep)->tag |= TLB_ENTRY_GLOBAL)
-#define	TLB_CLEAR_GLOBAL(ep)	((ep)->tag &= ~TLB_ENTRY_GLOBAL)
-#endif
-
-
-#if CPU_FAMILY == 4
-#define	NTLB	1
-#define	NENTRY	8
-#define	NWAY	4
-
-#define	TLB_ENTRY_SHIFT	12
-#define	TLB_WAY_SHIFT	14
-#endif
-
-typedef struct {
-	TLB_ENTRY_T	entry[NENTRY][NWAY];
-} TLB_T;
-
-static TLB_T tlb;
-
-
 void
 tlb_init(void)
 {
 
-	memset(&tlb, 0, sizeof(tlb));
+	memset(tlb, 0, sizeof(tlb));
 #if defined(IA32_PROFILE_TLB)
-	memset(&tlb_profile, 0, sizeof(tlb_profile));
+	memset(tlb_profile, 0, sizeof(tlb_profile));
 #endif	/* IA32_PROFILE_TLB */
 }
 
-void
+void MEMCALL
 tlb_flush(BOOL allflush)
 {
 	TLB_ENTRY_T *ep;
-	int i, j;
+	int i;
+	int n;
 
 	if (allflush) {
 		PROFILE_INC(tlb_global_flushes);
@@ -540,85 +821,104 @@ tlb_flush(BOOL allflush)
 		PROFILE_INC(tlb_flushes);
 	}
 
-	for (i = 0; i < NENTRY ; i++) {
-		for (j = 0; j < NWAY; j++) {
-			ep = &tlb.entry[i][j];
+	for (n = 0; n < NTLB; n++) {
+		for (i = 0; i < NENTRY ; i++) {
+			ep = &tlb[n].entry[i];
 			if (TLB_IS_VALID(ep) && (allflush || !TLB_IS_GLOBAL(ep))) {
-				TLB_CLEAR_VALID(ep);
+				TLB_SET_INVALID(ep);
 				PROFILE_INC(tlb_entry_flushes);
 			}
 		}
 	}
 }
 
-void
+void MEMCALL
 tlb_flush_page(UINT32 laddr)
 {
 	TLB_ENTRY_T *ep;
 	int idx;
-	int way;
+	int n;
 
 	PROFILE_INC(tlb_flushes);
 
-	idx = (laddr >> TLB_ENTRY_SHIFT) & (NENTRY - 1);
-	way = (laddr >> TLB_WAY_SHIFT) & (NWAY - 1);
-	ep = &tlb.entry[idx][way];
+	idx = (laddr >> TLB_ENTRY_SHIFT) & TLB_ENTRY_MASK;
 
-	if (TLB_IS_VALID(ep)) {
-		if ((laddr & TLB_TAG_MASK) == TLB_GET_TAG_ADDR(ep)) {
-			TLB_CLEAR_VALID(ep);
-			return;
+	for (n = 0; n < NTLB; n++) {
+		ep = &tlb[n].entry[idx];
+		if (TLB_IS_VALID(ep)) {
+			if ((laddr & TLB_TAG_MASK) == TLB_GET_TAG_ADDR(ep)) {
+				TLB_SET_INVALID(ep);
+				PROFILE_INC(tlb_entry_flushes);
+			}
 		}
 	}
 }
 
-static BOOL
-tlb_lookup(UINT32 laddr, int crw, UINT32 *paddr)
+TLB_ENTRY_T * MEMCALL
+tlb_lookup(const UINT32 laddr, const int ucrw)
 {
 	TLB_ENTRY_T *ep;
+	UINT bit;
 	int idx;
-	int way;
+	int n;
 
 	PROFILE_INC(tlb_lookups);
 
-	idx = (laddr >> TLB_ENTRY_SHIFT) & (NENTRY - 1);
-	way = (laddr >> TLB_WAY_SHIFT) & (NWAY - 1);
-	ep = &tlb.entry[idx][way];
+	n = (ucrw & CPU_PAGE_CODE) >> 1;
+	idx = (laddr >> TLB_ENTRY_SHIFT) & TLB_ENTRY_MASK;
+	ep = &tlb[n].entry[idx];
 
-	ep = &tlb.entry[idx][way];
 	if (TLB_IS_VALID(ep)) {
 		if ((laddr & TLB_TAG_MASK) == TLB_GET_TAG_ADDR(ep)) {
-			*paddr = TLB_GET_PADDR(ep, laddr);
-			PROFILE_INC(tlb_hits);
-			return TRUE;
+			bit = ucrw & (CPU_PAGE_WRITE|CPU_PAGE_USER_MODE);
+			bit |= ep->tag & (CPU_PTE_WRITABLE|CPU_PTE_USER_MODE);
+			bit |= CPU_STAT_WP;
+#if !defined(USE_PAGE_ACCESS_TABLE)
+			if ((page_access & (1 << bit)))
+#else
+			if (page_access_bit[bit])
+#endif
+			{
+				if (!(ucrw & CPU_PAGE_WRITE) || TLB_IS_DIRTY(ep)) {
+					PROFILE_INC(tlb_hits);
+					return ep;
+				}
+			}
 		}
 	}
-	(void)crw;
 	PROFILE_INC(tlb_misses);
-	return FALSE;
+	return NULL;
 }
 
-static void
-tlb_update(UINT32 laddr, UINT entry, int crw)
+static void MEMCALL
+tlb_update(const UINT32 laddr, const UINT entry, const int bit)
 {
 	TLB_ENTRY_T *ep;
+	UINT32 pos;
 	int idx;
-	int way;
+	int n;
 
 	PROFILE_INC(tlb_updates);
 
-	idx = (laddr >> TLB_ENTRY_SHIFT) & (NENTRY - 1);
-	way = (laddr >> TLB_WAY_SHIFT) & (NWAY - 1);
-	ep = &tlb.entry[idx][way];
+	n = bit & 1;
+	idx = (laddr >> TLB_ENTRY_SHIFT) & TLB_ENTRY_MASK;
+	ep = &tlb[n].entry[idx];
 
 	TLB_SET_VALID(ep);
-#if CPU_FAMILY >= 5
-	if (entry & CPU_PTE_GLOBAL_PAGE) {
-		TLB_SET_GLOBAL(ep);
-	}
-#endif
 	TLB_SET_TAG_ADDR(ep, laddr);
 	TLB_SET_PADDR(ep, entry);
-	(void)crw;
+	TLB_SET_TAG_FLAGS(ep, entry, bit);
+
+	if (ep->paddr < CPU_MEMREADMAX) {
+		ep->memp = mem + ep->paddr;
+		return;
+	} else if (ep->paddr >= USE_HIMEM) {
+		pos = (ep->paddr & CPU_ADRSMASK) - 0x100000;
+		if (pos < CPU_EXTMEMSIZE) {
+			ep->memp = CPU_EXTMEM + pos;
+			return;
+		}
+	}
+	ep->memp = NULL;
 }
 #endif	/* IA32_SUPPORT_TLB */