--- np2/i386c/ia32/paging.c 2004/01/13 16:37:42 1.3 +++ np2/i386c/ia32/paging.c 2004/03/24 14:34:23 1.22 @@ -1,7 +1,7 @@ -/* $Id: paging.c,v 1.3 2004/01/13 16:37:42 monaka Exp $ */ +/* $Id: paging.c,v 1.22 2004/03/24 14:34:23 monaka Exp $ */ /* - * Copyright (c) 2003 NONAKA Kimihiro + * Copyright (c) 2003-2004 NONAKA Kimihiro * All rights reserved. * * Redistribution and use in source and binary forms, with or without @@ -32,93 +32,6 @@ #include "ia32.mcr" /* - * ページ・ディレクトリ・エントリ (4K バイトページ使用時) - * - * 31 12 11 9 8 7 6 5 4 3 2 1 0 - * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+ - * | ページ・テーブルのベース・アドレス |使用可|G|PS|0|A|PCD|PWT|U/S|R/W|P| - * +----------------------------------------+------+-+--+-+-+---+---+---+---+-+ - * | | | | | | | | | | - * 9-11: システム・プログラマが使用可能 --------+ | | | | | | | | | - * 8: グローバル・ページ(無視される) ------------+ | | | | | | | | - * 7: ページ・サイズ (0 = 4k バイトページ) ---------+ | | | | | | | - * 6: 予約 (0) ---------------------------------------+ | | | | | | - * 5: アクセス -----------------------------------------+ | | | | | - * 4: キャッシュ無効 --------------------------------------+ | | | | - * 3: ライトスルー --------------------------------------------+ | | | - * 2: ユーザ／スーパバイザ (0 = スーパバイザ) ---------------------+ | | - * 1: 読み取り／書き込み (0 = 読み取りのみ) ---------------------------+ | - * 0: ページ存在 ---------------------------------------------------------+ - */ -#define CPU_PDE_BASEADDR_MASK 0xfffff000 -#define CPU_PDE_PAGE_SIZE (1 << 7) -#define CPU_PDE_ACCESS (1 << 5) -#define CPU_PDE_CACHE_DISABLE (1 << 4) -#define CPU_PDE_WRITE_THROUGH (1 << 3) -#define CPU_PDE_USER_MODE (1 << 2) -#define CPU_PDE_WRITABLE (1 << 1) -#define CPU_PDE_PRESENT (1 << 0) - -/* - * ページ・ディレクトリ・エントリ (4M バイトページ使用時) - * - * 31 22 21 12 11 9 8 7 6 5 4 3 2 1 0 - * +----------------------------+-----------+------+-+--+-+-+---+---+---+---+-+ - * |ページテーブルの物理アドレス| 予約済み |使用可|G|PS|D|A|PCD|PWT|U/S|R/W|P| - * +----------------------------+-----------+------+-+--+-+-+---+---+---+---+-+ - * | | | | | | | | | | - * 9-11: システム・プログラマが使用可能 --------+ | | | | | | | | | - * 8: グローバル・ページ ------------------------+ | | | | | | | | - * 7: ページ・サイズ (1 = 4M バイトページ) ---------+ | | | | | | | - * 6: ダーティ ---------------------------------------+ | | | | | | - * 5: アクセス -----------------------------------------+ | | | | | - * 4: キャッシュ無効 --------------------------------------+ | | | | - * 3: ライトスルー --------------------------------------------+ | | | - * 2: ユーザ／スーパバイザ (0 = スーパバイザ) ---------------------+ | | - * 1: 読み取り／書き込み (0 = 読み取りのみ) ---------------------------+ | - * 0: ページ存在 ---------------------------------------------------------+ - */ -#define CPU_PDE_4M_BASEADDR_MASK 0xffc00000 -#define CPU_PDE_4M_GLOBAL_PAGE (1 << 8) -#define CPU_PDE_4M_PAGE_SIZE (1 << 7) -#define CPU_PDE_4M_DIRTY (1 << 6) -#define CPU_PDE_4M_ACCESS (1 << 5) -#define CPU_PDE_4M_CACHE_DISABLE (1 << 4) -#define CPU_PDE_4M_WRITE_THROUGH (1 << 3) -#define CPU_PDE_4M_USER_MODE (1 << 2) -#define CPU_PDE_4M_WRITABLE (1 << 1) -#define CPU_PDE_4M_PRESENT (1 << 0) - -/* - * ページ・テーブル・エントリ (4k バイト・ページ) - * - * 31 12 11 9 8 7 6 5 4 3 2 1 0 - * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+ - * | ページのベース・アドレス |使用可|G|0|D|A|PCD|PWT|U/S|R/W|P| - * +----------------------------------------+------+-+-+-+-+---+---+---+---+-+ - * | | | | | | | | | | - * 9-11: システム・プログラマが使用可能 -------+ | | | | | | | | | - * 8: グローバル・ページ -----------------------+ | | | | | | | | - * 7: 予約 (0) -----------------------------------+ | | | | | | | - * 6: ダーティ -------------------------------------+ | | | | | | - * 5: アクセス ---------------------------------------+ | | | | | - * 4: キャッシュ無効 ------------------------------------+ | | | | - * 3: ライトスルー ------------------------------------------+ | | | - * 2: ユーザ／スーパバイザ (0 = スーパバイザ) -------------------+ | | - * 1: 読み取り／書き込み (0 = 読み取りのみ) -------------------------+ | - * 0: ページ存在 -------------------------------------------------------+ - */ -#define CPU_PTE_BASEADDR_MASK 0xfffff000 -#define CPU_PTE_GLOBAL_PAGE (1 << 8) -#define CPU_PTE_DIRTY (1 << 6) -#define CPU_PTE_ACCESS (1 << 5) -#define CPU_PTE_CACHE_DISABLE (1 << 4) -#define CPU_PTE_WRITE_THROUGH (1 << 3) -#define CPU_PTE_USER_MODE (1 << 2) -#define CPU_PTE_WRITABLE (1 << 1) -#define CPU_PTE_PRESENT (1 << 0) - -/* * ページフォルト例外 * * 4-31: 予約済み @@ -199,9 +112,9 @@ * +-----+-----------+-----+-----+---+ */ #if !defined(USE_PAGE_ACCESS_TABLE) -static const DWORD page_access = 0xd0cdd0ff; +#define page_access 0xd0ddd0ff #else /* USE_PAGE_ACCESS_TABLE */ -static const BYTE page_access_bit[32] = { +static const UINT8 page_access_bit[32] = { 1, /* CR0: n, CPL: s, PTE: s, PTE: r, ope: r */ 1, /* CR0: n, CPL: s, PTE: s, PTE: r, ope: w */ 1, /* CR0: n, CPL: s, PTE: s, PTE: w, ope: r */ @@ -230,7 +143,7 @@ static const BYTE page_access_bit[32] = 1, /* CR0: p, CPL: s, PTE: u, PTE: r, ope: r */ 0, /* CR0: p, CPL: s, PTE: u, PTE: r, ope: w */ 1, /* CR0: p, CPL: s, PTE: u, PTE: w, ope: r */ - 0, /* CR0: p, CPL: s, PTE: u, PTE: w, ope: w */ + 1, /* CR0: p, CPL: s, PTE: u, PTE: w, ope: w */ 0, /* CR0: p, CPL: u, PTE: s, PTE: r, ope: r */ 0, /* CR0: p, CPL: u, PTE: s, PTE: r, ope: w */ @@ -271,157 +184,524 @@ static const BYTE page_access_bit[32] = * +- CR3(物理アドレス) */ -static DWORD paging(DWORD laddr, int crw, int user_mode); +static UINT32 paging(const UINT32 laddr, const int ucrw); #if defined(IA32_SUPPORT_TLB) -static BOOL tlb_lookup(DWORD vaddr, int crw, DWORD* paddr); -static void tlb_update(DWORD paddr, DWORD entry, int crw); +static BOOL tlb_lookup(const UINT32 vaddr, const int crw, UINT32 *paddr); +static void tlb_update(const UINT32 laddr, const UINT entry, const int crw); #endif +#if defined(IA32_PAGING_EACHSIZE) +UINT8 MEMCALL +cpu_memory_access_la_RMW_b(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg) +{ + const int ucrw = CPU_PAGE_WRITE|CPU_PAGE_DATA|CPU_STAT_USER_MODE; + UINT32 result, value; + UINT32 paddr; + + paddr = paging(laddr, ucrw); + value = cpu_memoryread(paddr); + result = (*func)(value, arg); + cpu_memorywrite(paddr, (UINT8)result); + + return value; +} -DWORD MEMCALL -cpu_linear_memory_read(DWORD laddr, DWORD length, int code) +UINT16 MEMCALL +cpu_memory_access_la_RMW_w(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg) { - DWORD paddr; - DWORD remain; /* page remain */ - DWORD r; - DWORD value = 0; - int crw; - int pl; - - crw = CPU_PAGING_PAGE_READ; - crw |= code ? CPU_PAGING_PAGE_CODE : CPU_PAGING_PAGE_DATA; - pl = (CPU_STAT_CPL == 3); + const int ucrw = CPU_PAGE_WRITE|CPU_PAGE_DATA|CPU_STAT_USER_MODE; + UINT32 result, value; + UINT32 paddr[2]; + + paddr[0] = paging(laddr, ucrw); + if ((laddr + 1) & 0x00000fff) { + value = cpu_memoryread_w(paddr[0]); + result = (*func)(value, arg); + cpu_memorywrite_w(paddr[0], (UINT16)result); + } else { + paddr[1] = paging(laddr + 1, ucrw); + value = cpu_memoryread_b(paddr[0]); + value += (UINT16)cpu_memoryread_b(paddr[1]) << 8; + result = (*func)(value, arg); + cpu_memorywrite(paddr[0], (UINT8)result); + cpu_memorywrite(paddr[1], (UINT8)(result >> 8)); + } + return value; +} + +UINT32 MEMCALL +cpu_memory_access_la_RMW_d(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg) +{ + const int ucrw = CPU_PAGE_WRITE|CPU_PAGE_DATA|CPU_STAT_USER_MODE; + UINT32 result, value; + UINT32 paddr[2]; + UINT remain; - /* XXX: 4MB pages... */ + paddr[0] = paging(laddr, ucrw); remain = 0x1000 - (laddr & 0x00000fff); - for (;;) { - paddr = paging(laddr, crw, pl); + if (remain >= 4) { + value = cpu_memoryread_d(paddr[0]); + result = (*func)(value, arg); + cpu_memorywrite_d(paddr[0], result); + } else { + paddr[1] = paging(laddr + remain, ucrw); + switch (remain) { + case 3: + value = cpu_memoryread(paddr[0]); + value += (UINT32)cpu_memoryread_w(paddr[0] + 1) << 8; + value += (UINT32)cpu_memoryread(paddr[1]) << 24; + result = (*func)(value, arg); + cpu_memorywrite(paddr[0], (UINT8)result); + cpu_memorywrite_w(paddr[0] + 1, (UINT16)(result >> 8)); + cpu_memorywrite(paddr[1], (UINT8)(result >> 24)); + break; + + case 2: + value = cpu_memoryread_w(paddr[0]); + value += (UINT32)cpu_memoryread_w(paddr[1]) << 16; + result = (*func)(value, arg); + cpu_memorywrite_w(paddr[0], (UINT16)result); + cpu_memorywrite_w(paddr[1], (UINT16)(result >> 16)); + break; - r = (remain > length) ? length : remain; - switch (r) { case 1: - value = (value << 8) | cpu_memoryread(paddr); + value = cpu_memoryread(paddr[0]); + value += (UINT32)cpu_memoryread_w(paddr[1]) << 8; + value += (UINT32)cpu_memoryread(paddr[1] + 2) << 24; + result = (*func)(value, arg); + cpu_memorywrite(paddr[0], (UINT8)result); + cpu_memorywrite_w(paddr[1], (UINT16)(result >> 8)); + cpu_memorywrite(paddr[1] + 2, (UINT8)(result >> 24)); break; - case 2: - value = (value << 16) | cpu_memoryread_w(paddr); + default: + ia32_panic("cpu_memory_access_la_RMW_d(): out of range (remain = %d)\n", remain); + value = 0; /* compiler happy */ break; + } + } + return value; +} + +UINT8 MEMCALL +cpu_linear_memory_read_b(UINT32 laddr, const int ucrw) +{ + UINT32 addr; + + addr = paging(laddr, ucrw); + return cpu_memoryread(addr); +} + +UINT16 MEMCALL +cpu_linear_memory_read_w(UINT32 laddr, const int ucrw) +{ + UINT32 addr, addr2; + UINT16 value; + + addr = paging(laddr, ucrw); + if ((laddr + 1) & 0x00000fff) { + return cpu_memoryread_w(addr); + } else { + addr2 = paging(laddr + 1, ucrw); + value = cpu_memoryread_b(addr); + value += (UINT16)cpu_memoryread_b(addr2) << 8; + return value; + } +} + +UINT32 MEMCALL +cpu_linear_memory_read_d(UINT32 laddr, const int ucrw) +{ + UINT32 addr, addr2; + UINT32 value; + UINT remain; + addr = paging(laddr, ucrw); + remain = 0x1000 - (laddr & 0x00000fff); + if (remain >= 4) { + return cpu_memoryread_d(addr); + } else { + addr2 = paging(laddr + remain, ucrw); + switch (remain) { case 3: - value <<= 24; - value |= cpu_memoryread_w(paddr) << 8; - value |= cpu_memoryread(paddr + 2); + value = cpu_memoryread(addr); + value += (UINT32)cpu_memoryread_w(addr + 1) << 8; + value += (UINT32)cpu_memoryread(addr2) << 24; break; - case 4: - value = cpu_memoryread_d(paddr); + case 2: + value = cpu_memoryread_w(addr); + value += (UINT32)cpu_memoryread_w(addr2) << 16; break; - default: - ia32_panic("cpu_linear_memory_read(): out of range\n"); + case 1: + value = cpu_memoryread(addr); + value += (UINT32)cpu_memoryread(addr2) << 8; + value += (UINT32)cpu_memoryread_w(addr2 + 1) << 16; break; - } - if (length == r) + default: + ia32_panic("cpu_linear_memory_read_d(): out of range (remain = %d)\n", remain); + value = 0; /* compiler happy */ break; - - length -= r; - remain -= r; - laddr += r; + } + return value; } +} - return value; +void MEMCALL +cpu_linear_memory_write_b(UINT32 laddr, UINT8 value, const int user_mode) +{ + const int ucrw = CPU_PAGE_WRITE|CPU_PAGE_DATA|user_mode; + UINT32 addr; + + addr = paging(laddr, ucrw); + cpu_memorywrite(addr, value); } void MEMCALL -cpu_linear_memory_write(DWORD laddr, DWORD length, DWORD value) +cpu_linear_memory_write_w(UINT32 laddr, UINT16 value, const int user_mode) { - DWORD paddr; - DWORD remain; /* page remain */ - DWORD r; - int pl; + const int ucrw = CPU_PAGE_WRITE|CPU_PAGE_DATA|user_mode; + UINT32 addr, addr2; - pl = (CPU_STAT_CPL == 3); + addr = paging(laddr, ucrw); + if ((laddr + 1) & 0x00000fff) { + cpu_memorywrite_w(addr, value); + } else { + addr2 = paging(laddr + 1, ucrw); + cpu_memorywrite(addr, (UINT8)value); + cpu_memorywrite(addr2, (UINT8)(value >> 8)); + } +} - /* XXX: 4MB pages... */ +void MEMCALL +cpu_linear_memory_write_d(UINT32 laddr, UINT32 value, const int user_mode) +{ + const int ucrw = CPU_PAGE_WRITE|CPU_PAGE_DATA|user_mode; + UINT32 addr, addr2; + UINT remain; + + addr = paging(laddr, ucrw); remain = 0x1000 - (laddr & 0x00000fff); - for (;;) { - paddr = paging(laddr, CPU_PAGING_PAGE_WRITE|CPU_PAGING_PAGE_DATA, pl); + if (remain >= 4) { + cpu_memorywrite_d(addr, value); + } else { + addr2 = paging(laddr + remain, ucrw); + switch (remain) { + case 3: + cpu_memorywrite(addr, (UINT8)value); + cpu_memorywrite_w(addr + 1, (UINT16)(value >> 8)); + cpu_memorywrite(addr2, (UINT8)(value >> 24)); + break; + + case 2: + cpu_memorywrite_w(addr, (UINT16)value); + cpu_memorywrite_w(addr2, (UINT16)(value >> 16)); + break; - r = (remain > length) ? length : remain; - switch (r) { case 1: - cpu_memorywrite(paddr, value); - value >>= 8; + cpu_memorywrite(addr, (UINT8)value); + cpu_memorywrite(addr2, (UINT8)(value >> 8)); + cpu_memorywrite_w(addr2 + 1, (UINT16)(value >> 16)); + break; + } + } +} + +#else /* !IA32_PAGING_EACHSIZE */ + +UINT32 MEMCALL +cpu_memory_access_la_RMW(UINT32 laddr, UINT length, UINT32 (*func)(UINT32, void *), void *arg) +{ + const int ucrw = CPU_PAGE_WRITE|CPU_PAGE_DATA|CPU_STAT_USER_MODE; + UINT32 result, value; + UINT32 paddr[2]; + UINT remain; + + paddr[0] = paging(laddr, ucrw); + remain = 0x1000 - (laddr & 0x00000fff); + if (remain >= length) { + /* fast mode */ + switch (length) { + case 4: + value = cpu_memoryread_d(paddr[0]); + result = (*func)(value, arg); + cpu_memorywrite_d(paddr[0], result); break; case 2: - cpu_memorywrite_w(paddr, value); - value >>= 16; + value = cpu_memoryread_w(paddr[0]); + result = (*func)(value, arg); + cpu_memorywrite_w(paddr[0], (UINT16)result); break; - case 3: - cpu_memorywrite_w(paddr, value); - cpu_memorywrite(paddr, value >> 16); - value >>= 24; + case 1: + value = cpu_memoryread(paddr[0]); + result = (*func)(value, arg); + cpu_memorywrite(paddr[0], (UINT8)result); + break; + + default: + ia32_panic("cpu_memory_access_la_RMW(): invalid length (length = %d)\n", length); + value = 0; /* compiler happy */ break; + } + return value; + } + + /* slow mode */ + paddr[1] = paging(laddr + remain, ucrw); + switch (remain) { + case 3: + value = cpu_memoryread(paddr[0]); + value += (UINT32)cpu_memoryread_w(paddr[0] + 1) << 8; + value += (UINT32)cpu_memoryread(paddr[1]) << 24; + result = (*func)(value, arg); + cpu_memorywrite(paddr[0], (UINT8)result); + cpu_memorywrite_w(paddr[0] + 1, (UINT16)(result >> 8)); + cpu_memorywrite(paddr[1], (UINT8)(result >> 24)); + break; + + case 2: + value = cpu_memoryread_w(paddr[0]); + value += (UINT32)cpu_memoryread_w(paddr[1]) << 16; + result = (*func)(value, arg); + cpu_memorywrite_w(paddr[0], (UINT16)result); + cpu_memorywrite_w(paddr[1], (UINT16)(result >> 16)); + break; + + case 1: + value = cpu_memoryread(paddr[0]); + value += (UINT32)cpu_memoryread(paddr[1]) << 8; + if (length == 4) { + value += (UINT32)cpu_memoryread_w(paddr[1] + 1) << 16; + } + result = (*func)(value, arg); + cpu_memorywrite(paddr[0], (UINT8)result); + cpu_memorywrite(paddr[1], (UINT8)(result >> 8)); + if (length == 4) { + cpu_memorywrite_w(paddr[1] + 1, (UINT16)(result >> 16)); + } + break; + + default: + ia32_panic("cpu_memory_access_la_RMW(): out of range (remain = %d)\n", remain); + value = 0; /* compiler happy */ + break; + } + return value; +} +UINT32 MEMCALL +cpu_linear_memory_read(UINT32 laddr, UINT length, const int ucrw) +{ + UINT32 value; + UINT32 paddr[2]; + UINT remain; + + paddr[0] = paging(laddr, ucrw); + remain = 0x1000 - (laddr & 0x00000fff); + if (remain >= length) { + /* fast mode */ + switch (length) { case 4: - cpu_memorywrite_d(paddr, value); + value = cpu_memoryread_d(paddr[0]); + break; + + case 2: + value = cpu_memoryread_w(paddr[0]); + break; + + case 1: + value = cpu_memoryread(paddr[0]); break; default: - ia32_panic("cpu_linear_memory_write(): out of range\n"); + ia32_panic("cpu_linear_memory_read(): invalid length (length = %d)\n", length); + value = 0; /* compiler happy */ break; } + return value; + } + + /* slow mode */ + paddr[1] = paging(laddr + remain, ucrw); + switch (remain) { + case 3: + value = cpu_memoryread(paddr[0]); + value += (UINT32)cpu_memoryread_w(paddr[0] + 1) << 8; + value += (UINT32)cpu_memoryread(paddr[1]) << 24; + break; + + case 2: + value = cpu_memoryread_w(paddr[0]); + value += (UINT32)cpu_memoryread_w(paddr[1]) << 16; + break; + + case 1: + value = cpu_memoryread(paddr[0]); + value += (UINT32)cpu_memoryread(paddr[1]) << 8; + if (length == 4) { + value += (UINT32)cpu_memoryread_w(paddr[1] + 1) << 16; + } + break; + + default: + ia32_panic("cpu_linear_memory_read(): out of range (remain = %d)\n", remain); + value = 0; /* compiler happy */ + break; + } + return value; +} + +void MEMCALL +cpu_linear_memory_write(UINT32 laddr, UINT32 value, UINT length, const int user_mode) +{ + const int ucrw = CPU_PAGE_WRITE|CPU_PAGE_DATA|user_mode; + UINT32 paddr[2]; + UINT remain; + + paddr[0] = paging(laddr, ucrw); + remain = 0x1000 - (laddr & 0x00000fff); + if (remain >= length) { + /* fast mode */ + switch (length) { + case 4: + cpu_memorywrite_d(paddr[0], value); + break; + + case 2: + cpu_memorywrite_w(paddr[0], (UINT16)value); + break; + + case 1: + cpu_memorywrite(paddr[0], (UINT8)value); + break; - if (length == r) + default: + ia32_panic("cpu_linear_memory_write(): invalid length (length = %d)\n", length); break; + } + return; + } + + /* slow mode */ + paddr[1] = paging(laddr + remain, ucrw); + switch (remain) { + case 3: + cpu_memorywrite(paddr[0], (UINT8)value); + cpu_memorywrite_w(paddr[0] + 1, (UINT16)(value >> 8)); + cpu_memorywrite(paddr[1], (UINT8)(value >> 24)); + break; + + case 2: + cpu_memorywrite_w(paddr[0], (UINT16)value); + cpu_memorywrite_w(paddr[1], (UINT16)(value >> 16)); + break; + + case 1: + cpu_memorywrite(paddr[0], (UINT8)value); + cpu_memorywrite(paddr[1], (UINT8)(value >> 8)); + if (length == 4) { + cpu_memorywrite_w(paddr[1] + 1, (UINT16)(value >> 16)); + } + break; + + default: + ia32_panic("cpu_linear_memory_write(): out of range (remain = %d)\n", remain); + break; + } +} +#endif /* IA32_PAGING_EACHSIZE */ + +void MEMCALL +cpu_memory_access_la_region(UINT32 laddr, UINT length, const int ucrw, BYTE *data) +{ + UINT32 paddr; + UINT remain; /* page remain */ + UINT r; + + if (length == 0) + return; + + remain = 0x1000 - (laddr & 0x00000fff); + for (;;) { + if (!CPU_STAT_PAGING) { + paddr = laddr; + } else { + paddr = paging(laddr, ucrw); + } + + r = (remain > length) ? length : remain; + if (!(ucrw & CPU_PAGE_WRITE)) { + cpu_memoryread_region(paddr, data, r); + } else { + cpu_memorywrite_region(paddr, data, r); + } length -= r; - remain -= r; + if (length == 0) + break; + + data += r; laddr += r; + remain -= r; + if (remain <= 0) { + /* next page */ + remain += 0x1000; + } } } void MEMCALL -paging_check(DWORD laddr, DWORD length, int rw) +paging_check(UINT32 laddr, UINT length, const int ucrw) +{ + UINT32 paddr; + UINT remain; /* page remain */ + UINT r; + + remain = 0x1000 - (laddr & 0x00000fff); + for (;;) { + paddr = paging(laddr, ucrw); + + r = (remain > length) ? length : remain; + + length -= r; + if (length == 0) + break; + + laddr += r; + remain -= r; + if (remain <= 0) { + /* next page */ + remain += 0x1000; + } + } +} + +static UINT32 +paging(const UINT32 laddr, const int ucrw) { - DWORD addr; - int n; - int pl; - - pl = (CPU_STAT_CPL == 3); - - /* XXX: 4MB pages... */ - n = ((laddr & 0xfff) + length) / 0x1000; - addr = (laddr & ~0xfff); - do { - (void)paging(addr, rw, pl); - addr += 0x1000; - } while (--n > 0); -} - -static DWORD -paging(DWORD laddr, int crw, int user_mode) -{ - DWORD paddr; /* physical address */ - DWORD pde_addr; /* page directory entry address */ - DWORD pde; /* page directory entry */ - DWORD pte_addr; /* page table entry address */ - DWORD pte; /* page table entry */ - DWORD bit; - DWORD err = 0; + UINT32 paddr; /* physical address */ + UINT32 pde_addr; /* page directory entry address */ + UINT32 pde; /* page directory entry */ + UINT32 pte_addr; /* page table entry address */ + UINT32 pte; /* page table entry */ + UINT bit; + UINT err; #if defined(IA32_SUPPORT_TLB) if (tlb_lookup(laddr, crw, &paddr)) return paddr; #endif /* IA32_SUPPORT_TLB */ - pde_addr = (CPU_CR3 & CPU_CR3_PD_MASK) | ((laddr >> 20) & 0xffc); + pde_addr = CPU_STAT_PDE_BASE + ((laddr >> 20) & 0xffc); pde = cpu_memoryread_d(pde_addr); if (!(pde & CPU_PDE_PRESENT)) { - VERBOSE(("PDE is not present. (laddr = 0x%08x, pde_addr = 0x%08x, pde = 0x%08x)", laddr, pde_addr, pde)); + VERBOSE(("paging: PTE page is not present")); + VERBOSE(("paging: CPU_CR3 = 0x%08x", CPU_CR3)); + VERBOSE(("paging: laddr = 0x%08x, pde_addr = 0x%08x, pde = 0x%08x", laddr, pde_addr, pde)); err = 0; goto pf_exception; } @@ -430,40 +710,27 @@ paging(DWORD laddr, int crw, int user_mo cpu_memorywrite_d(pde_addr, pde); } - /* no support PAE */ - __ASSERT(!(CPU_CR4 & CPU_CR4_PAE)); - - if ((CPU_CR4 & CPU_CR4_PSE) && (pde & CPU_PDE_PAGE_SIZE)) { - /* 4MB page size */ - - /* fake PTE bit */ - pte = pde | CPU_PTE_DIRTY; - pte_addr = 0; /* compiler happy */ - - /* make physical address */ - paddr = (pde & CPU_PDE_4M_BASEADDR_MASK) | (laddr & 0x003fffff); - } else { - /* 4KB page size */ - pte_addr = (pde & CPU_PDE_BASEADDR_MASK) | ((laddr >> 10) & 0xffc); - pte = cpu_memoryread_d(pte_addr); - if (!(pte & CPU_PTE_PRESENT)) { - VERBOSE(("PTE is not present. (laddr = 0x%08x, pde_addr = 0x%08x, pde = 0x%08x, pte_addr = 0x%08x, pte = 0x%08x)", laddr, pde_addr, pde, pte_addr, pte)); - err = 0; - goto pf_exception; - } - if (!(pte & CPU_PTE_ACCESS)) { - pte |= CPU_PTE_ACCESS; - cpu_memorywrite_d(pte_addr, pte); - } - - /* make physical address */ - paddr = (pte & CPU_PTE_BASEADDR_MASK) | (laddr & 0x00000fff); + pte_addr = (pde & CPU_PDE_BASEADDR_MASK) + ((laddr >> 10) & 0xffc); + pte = cpu_memoryread_d(pte_addr); + if (!(pte & CPU_PTE_PRESENT)) { + VERBOSE(("paging: page is not present")); + VERBOSE(("paging: laddr = 0x%08x, pde_addr = 0x%08x, pde = 0x%08x", laddr, pde_addr, pde)); + VERBOSE(("paging: pte_addr = 0x%08x, pte = 0x%08x", pte_addr, pte)); + err = 0; + goto pf_exception; } + if (!(pte & CPU_PTE_ACCESS)) { + pte |= CPU_PTE_ACCESS; + cpu_memorywrite_d(pte_addr, pte); + } + + /* make physical address */ + paddr = (pte & CPU_PTE_BASEADDR_MASK) + (laddr & 0x00000fff); - bit = crw & 1; + bit = ucrw & CPU_PAGE_WRITE; bit |= (pde & pte & (CPU_PTE_WRITABLE|CPU_PTE_USER_MODE)); - bit |= (user_mode << 3); - bit |= (CPU_CR0 & CPU_CR0_WP) >> 12; + bit |= ucrw & CPU_PAGE_USER_MODE; + bit |= CPU_STAT_WP; #if !defined(USE_PAGE_ACCESS_TABLE) if (!(page_access & (1 << bit))) @@ -471,126 +738,122 @@ paging(DWORD laddr, int crw, int user_mo if (!(page_access_bit[bit])) #endif { - VERBOSE(("page access violation. (laddr = 0x%08x, pde_addr = 0x%08x, pde = 0x%08x, pte_addr = 0x%08x, pte = 0x%08x, paddr = 0x%08x, bit = 0x%08x)", laddr, pde_addr, pde, pte_addr, pte, paddr, bit)); + VERBOSE(("paging: page access violation.")); + VERBOSE(("paging: laddr = 0x%08x, pde_addr = 0x%08x, pde = 0x%08x", laddr, pde_addr, pde)); + VERBOSE(("paging: pte_addr = 0x%08x, pte = 0x%08x", pte_addr, pte)); + VERBOSE(("paging: paddr = 0x%08x, bit = 0x%08x", paddr, bit)); err = 1; goto pf_exception; } - if ((crw & 1) && !(pte & CPU_PTE_DIRTY)) { + if ((ucrw & CPU_PAGE_WRITE) && !(pte & CPU_PTE_DIRTY)) { pte |= CPU_PTE_DIRTY; cpu_memorywrite_d(pte_addr, pte); } #if defined(IA32_SUPPORT_TLB) - tlb_update(paddr, pte, crw); + tlb_update(laddr, pte, ucrw); #endif /* IA32_SUPPORT_TLB */ return paddr; pf_exception: CPU_CR2 = laddr; - err |= ((crw & 1) << 1) | (user_mode << 2); + err |= (ucrw & CPU_PAGE_WRITE) << 1; + err |= (ucrw & CPU_PAGE_USER_MODE) >> 1; EXCEPTION(PF_EXCEPTION, err); return 0; /* compiler happy */ } + #if defined(IA32_SUPPORT_TLB) /* * TLB */ +#if defined(IA32_PROFILE_TLB) +/* profiling */ typedef struct { - BYTE valid; /* TLB entry is valid */ - BYTE global; /* this TLB entry is global */ - BYTE score; - BYTE pad; + UINT64 tlb_hits; + UINT64 tlb_misses; + UINT64 tlb_lookups; + UINT64 tlb_updates; + UINT64 tlb_flushes; + UINT64 tlb_global_flushes; + UINT64 tlb_entry_flushes; +} TLB_PROFILE_T; - DWORD tag; - DWORD mask; /* 4K or 2M or 4M */ +static TLB_PROFILE_T tlb_profile; + +#define PROFILE_INC(v) tlb_profile.v++ +#else /* !IA32_PROFILE_TLB */ +#define PROFILE_INC(v) +#endif /* IA32_PROFILE_TLB */ - DWORD paddr; /* physical addr */ -} TLB_ENTRY_T; typedef struct { - BYTE kind; -#define TLB_KIND_INSTRUCTION (1 << 1) -#define TLB_KIND_DATA (1 << 2) -#define TLB_KIND_COMBINE (TLB_KIND_INSTRUCTION|TLB_KIND_DATA) -#define TLB_KIND_SMALL (1 << 3) -#define TLB_KIND_LARGE (1 << 4) -#define TLB_KIND_BOTH (TLB_KIND_SMALL|TLB_KIND_LARGE) - - BYTE way; /* n-way associative */ - BYTE idx; /* number of TLB index */ - BYTE bpad; + UINT32 tag; /* linear address */ +#define TLB_ENTRY_VALID (1 << 0) +#define TLB_ENTRY_GLOBAL CPU_PTE_GLOBAL_PAGE - WORD num; /* number of TLB entry */ - WORD wpad; + UINT32 paddr; /* physical address */ +} TLB_ENTRY_T; - TLB_ENTRY_T* entry; /* entry[assoc][idx] or entry[assoc] if idx == 1*/ -} TLB_T; +#define TLB_GET_PADDR(ep, addr) ((ep)->paddr + ((addr) & ~CPU_PTE_BASEADDR_MASK)) +#define TLB_SET_PADDR(ep, addr) ((ep)->paddr = (addr) & CPU_PTE_BASEADDR_MASK) -static int ntlb; -static TLB_T tlb[4]; /* i TLB, i (lp) TLB, d TLB, d (lp) TLB */ +#define TLB_TAG_SHIFT 17 +#define TLB_TAG_MASK ~((1 << TLB_TAG_SHIFT) - 1) +#define TLB_GET_TAG_ADDR(ep) ((ep)->tag & TLB_TAG_MASK) +#define TLB_SET_TAG_ADDR(ep, addr) \ + ((ep)->tag = ((addr) & TLB_TAG_MASK) + ((ep)->tag & ~TLB_TAG_MASK)) + +#define TLB_IS_VALID(ep) ((ep)->tag & TLB_ENTRY_VALID) +#define TLB_SET_VALID(ep) ((ep)->tag |= TLB_ENTRY_VALID) +#define TLB_CLEAR_VALID(ep) ((ep)->tag &= ~TLB_ENTRY_VALID) + +#if CPU_FAMILY == 4 +#define TLB_IS_GLOBAL(ep) FALSE +#define TLB_SET_GLOBAL(ep) (void)(ep) +#define TLB_CLEAR_GLOBAL(ep) (void)(ep) +#else +#define TLB_IS_GLOBAL(ep) ((ep)->tag & TLB_ENTRY_GLOBAL) +#define TLB_SET_GLOBAL(ep) ((ep)->tag |= TLB_ENTRY_GLOBAL) +#define TLB_CLEAR_GLOBAL(ep) ((ep)->tag &= ~TLB_ENTRY_GLOBAL) +#endif -#if defined(IA32_PROFILE_TLB) -/* profiling */ -static DWORD tlb_hits; -static DWORD tlb_misses; -static DWORD tlb_lookups; -static DWORD tlb_updates; -static DWORD tlb_flushes; -static DWORD tlb_global_flushes; -static DWORD tlb_entry_flushes; -#define PROFILE_INC(v) (v)++; -#else /* !IA32_PROFILE_TLB */ -#define PROFILE_INC(v) -#endif /* IA32_PROFILE_TLB */ +#if CPU_FAMILY == 4 +#define NTLB 1 +#define NENTRY (1 << 3) +#define NWAY (1 << 2) + +#define TLB_ENTRY_SHIFT 12 +#define TLB_ENTRY_MASK (NENTRY - 1) +#define TLB_WAY_SHIFT 15 +#define TLB_WAY_MASK (NWAY - 1) +#endif + +typedef struct { + TLB_ENTRY_T entry[NENTRY][NWAY]; +} TLB_T; + +static TLB_T tlb; + void -tlb_init() +tlb_init(void) { - int i; - - for (i = 0; i < NELEMENTS(tlb); i++) { - if (tlb[i].entry) { - free(tlb[i].entry); - } - } - memset(tlb, 0, sizeof(tlb)); + memset(&tlb, 0, sizeof(tlb)); #if defined(IA32_PROFILE_TLB) - tlb_hits = 0; - tlb_misses = 0; - tlb_lookups = 0; - tlb_updates = 0; - tlb_flushes = 0; - tlb_global_flushes = 0; - tlb_entry_flushes = 0; + memset(&tlb_profile, 0, sizeof(tlb_profile)); #endif /* IA32_PROFILE_TLB */ - - /* XXX プロセッサ種別にしたがって TLB 構成を構築する */ - - /* とりあえず i486 形式で… */ - /* combine (I/D) TLB: 4KB Pages, 4-way set associative 32 entries */ - ntlb = 1; - tlb[0].kind = TLB_KIND_COMBINE | TLB_KIND_SMALL; - tlb[0].num = 32; - tlb[0].way = 4; - tlb[0].idx = tlb[0].num / tlb[0].way; - - for (i = 0; i < ntlb; i++) { - tlb[i].entry = (TLB_ENTRY_T*)calloc(sizeof(TLB_ENTRY_T), tlb[i].num); - if (tlb[i].entry == 0) { - ia32_panic("tlb_init(): can't alloc TLB entry\n"); - } - } } void tlb_flush(BOOL allflush) { - TLB_ENTRY_T* ep; + TLB_ENTRY_T *ep; int i, j; if (allflush) { @@ -599,11 +862,11 @@ tlb_flush(BOOL allflush) PROFILE_INC(tlb_flushes); } - for (i = 0; i < ntlb; i++) { - ep = tlb[i].entry; - for (j = 0; j < tlb[i].num; j++, ep++) { - if (ep->valid && (allflush || !ep->global)) { - ep->valid = 0; + for (i = 0; i < NENTRY ; i++) { + for (j = 0; j < NWAY; j++) { + ep = &tlb.entry[i][j]; + if (TLB_IS_VALID(ep) && (!TLB_IS_GLOBAL(ep) || allflush)) { + TLB_CLEAR_VALID(ep); PROFILE_INC(tlb_entry_flushes); } } @@ -611,157 +874,73 @@ tlb_flush(BOOL allflush) } void -tlb_flush_page(DWORD vaddr) +tlb_flush_page(UINT32 laddr) { - TLB_ENTRY_T* ep; + TLB_ENTRY_T *ep; int idx; - int i; + int way; - for (i = 0; i < ntlb; i++) { - if (tlb[i].idx == 1) { - /* fully set associative */ - idx = 0; - } else { - if (tlb[i].kind & TLB_KIND_SMALL) { - idx = (vaddr >> 12) & (tlb[i].idx - 1); - } else { - idx = (vaddr >> 22) & (tlb[i].idx - 1); - } - } + PROFILE_INC(tlb_flushes); - /* search */ - ep = &tlb[i].entry[idx * tlb[i].way]; - for (i = 0; i < tlb[i].way; i++) { - if (ep->valid) { - if ((vaddr & ep->mask) == ep->tag) { - ep->valid = 0; - PROFILE_INC(tlb_entry_flushes); - break; - } - } + idx = (laddr >> TLB_ENTRY_SHIFT) & (NENTRY - 1); + way = (laddr >> TLB_WAY_SHIFT) & (NWAY - 1); + ep = &tlb.entry[idx][way]; + + if (TLB_IS_VALID(ep)) { + if ((laddr & TLB_TAG_MASK) == TLB_GET_TAG_ADDR(ep)) { + TLB_CLEAR_VALID(ep); + return; } } } static BOOL -tlb_lookup(DWORD laddr, int crw, DWORD* paddr) +tlb_lookup(const UINT32 laddr, const int crw, UINT32 *paddr) { - TLB_ENTRY_T* ep; + TLB_ENTRY_T *ep; int idx; - int i; + int way; PROFILE_INC(tlb_lookups); - crw &= CPU_PAGING_PAGE_CODE | CPU_PAGING_PAGE_DATA; - for (i = 0; i < ntlb; i++) { - if (tlb[i].kind & crw) { - if (tlb[i].idx == 1) { - /* fully set associative */ - idx = 0; - } else { - if (tlb[i].kind & TLB_KIND_SMALL) { - idx = (laddr >> 12) & (tlb[i].idx - 1); - } else { - idx = (laddr >> 22) & (tlb[i].idx - 1); - } - } - - /* search */ - ep = &tlb[i].entry[idx * tlb[i].way]; - for (i = 0; i < tlb[i].way; i++) { - if (ep->valid) { - if ((laddr & ep->mask) == ep->tag) { - if (ep->score != (BYTE)~0) - ep->score++; - *paddr = ep->paddr; - PROFILE_INC(tlb_hits); - return TRUE; - } - } - } + idx = (laddr >> TLB_ENTRY_SHIFT) & (NENTRY - 1); + way = (laddr >> TLB_WAY_SHIFT) & (NWAY - 1); + ep = &tlb.entry[idx][way]; + + ep = &tlb.entry[idx][way]; + if (TLB_IS_VALID(ep)) { + if ((laddr & TLB_TAG_MASK) == TLB_GET_TAG_ADDR(ep)) { + *paddr = TLB_GET_PADDR(ep, laddr); + PROFILE_INC(tlb_hits); + return TRUE; } } + (void)crw; PROFILE_INC(tlb_misses); return FALSE; } static void -tlb_update(DWORD paddr, DWORD entry, int crw) +tlb_update(const UINT32 laddr, const UINT entry, const int crw) { - TLB_ENTRY_T* ep; + TLB_ENTRY_T *ep; int idx; - int i, j; - int min_way; - WORD min_score = ~0; + int way; PROFILE_INC(tlb_updates); - crw &= CPU_PAGING_PAGE_CODE | CPU_PAGING_PAGE_DATA; - for (i = 0; i < ntlb; i++) { - if (tlb[i].kind & crw) { - if (tlb[i].idx == 1) { - /* fully set associative */ - idx = 0; - } else { - /* n-way set associative */ - if (!(entry & CPU_PDE_PAGE_SIZE)) { - if (!(tlb[i].kind & TLB_KIND_SMALL)) - continue; - idx = (entry >> 12) & (tlb[i].idx - 1); - } else { - if (!(tlb[i].kind & TLB_KIND_LARGE)) - continue; - idx = (entry >> 22) & (tlb[i].idx - 1); - } - } - - /* search */ - ep = &tlb[i].entry[idx * tlb[i].way]; - for (min_way = 0, j = 0; j < tlb[i].way; j++, ep++) { - if (ep->valid) { - if (min_score >= ep->score) { - min_way = j; - min_score = ep->score; - } - } else { - min_way = j; - min_score = 0; - break; - } - } - - /* replace */ - ep = &tlb[i].entry[idx * tlb[i].way + min_way]; - ep->valid = 1; - ep->global = (entry & CPU_PTE_GLOBAL_PAGE) ? 1 : 0; - ep->score = 0; - ep->mask = (entry & CPU_PDE_PAGE_SIZE) ? CPU_PDE_4M_BASEADDR_MASK : CPU_PTE_BASEADDR_MASK; - ep->tag = entry & ep->mask; - ep->paddr = paddr; - break; - } + idx = (laddr >> TLB_ENTRY_SHIFT) & (NENTRY - 1); + way = (laddr >> TLB_WAY_SHIFT) & (NWAY - 1); + ep = &tlb.entry[idx][way]; + + TLB_SET_VALID(ep); +#if CPU_FAMILY >= 5 + if (entry & CPU_PTE_GLOBAL_PAGE) { + TLB_SET_GLOBAL(ep); } - __ASSERT(i != ntlb); -} -#else /* !IA32_SUPPORT_TLB */ -void -tlb_init() -{ - - /* nothing to do */ -} - -void -tlb_flush(BOOL allflush) -{ - - (void)allflush; -} - -void -tlb_flush_page(DWORD laddr) -{ - - (void)laddr; +#endif + TLB_SET_TAG_ADDR(ep, laddr); + TLB_SET_PADDR(ep, entry); + (void)crw; } #endif /* IA32_SUPPORT_TLB */