--- np2/i386c/ia32/paging.c 2004/03/24 14:34:23 1.22 +++ np2/i386c/ia32/paging.c 2012/01/23 06:01:44 1.38 @@ -1,5 +1,3 @@ -/* $Id: paging.c,v 1.22 2004/03/24 14:34:23 monaka Exp $ */ - /* * Copyright (c) 2003-2004 NONAKA Kimihiro * All rights reserved. @@ -12,8 +10,6 @@ * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimer in the * documentation and/or other materials provided with the distribution. - * 3. The name of the author may not be used to endorse or promote products - * derived from this software without specific prior written permission. * * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES @@ -32,25 +28,25 @@ #include "ia32.mcr" /* - * ¡¦¥ì¡£¥·¡¦¥¯¡¦¥æ¡¦¥¥¡¦ö§¥Í¥Û浡¼ + * åãÔ妾å⥯åãÊ夫å㥩åã°æ¥»¶ç¡¢ * - * 4-31: ͽÌóºÑ¤ß - * 3: RSVD: 0 = ¥Õ¥©¥ë¥È¤Î¸¶°ø¤ÏͽÌó¥Ó¥Ã¥È°ãÈ¿¤Ç¤Ï¤Ê¤«¤Ã¤¿¡¥ - * 1 = ¥Ú¡¼¥¸¡¦¥Õ¥©¥ë¥È¤Î¸¶°ø¤Ï¡¤°ãÈ¿¤È¥Þ¡¼¥¯¤µ¤ì¤¿ PTE ¤Þ¤¿¤Ï - * PDE ¤ÎͽÌó¥Ó¥Ã¥È°ÌÃ֤Τ¦¤Á°ì¤Ä¤Ç¡¤1 ¤¬¸¡½Ð¤µ¤ì¤¿¤³¤È¤Ç¤¢¤ë¡¥ - * 2: U/S: 0 = ¥Õ¥©¥ë¥È¤Î¸¶°ø¤È¤Ê¤Ã¤¿¥¢¥¯¥»¥¹¤Ï¥×¥í¥»¥Ã¥µ¤¬¥¹¡¼¥Ñ¥Ð¥¤¥¶¡¦ - * ¥â¡¼¥É¤Ç¼Â¹ÔÃæ¤Ë¹Ô¤ï¤ì¤¿¡¥ - * 1 = ¥Õ¥©¥ë¥È¤Î¸¶°ø¤È¤Ê¤Ã¤¿¥¢¥¯¥»¥¹¤Ï¥×¥í¥»¥Ã¥µ¤¬¥æ¡¼¥¶¡¦¥â¡¼¥É¤Ç - * ¼Â¹ÔÃæ¤Ë¹Ô¤ï¤ì¤¿¡¥ - * 1: W/R: 0 = ¥Õ¥©¥ë¥È¤Î¸¶°ø¤È¤Ê¤Ã¤¿¥¢¥¯¥»¥¹¤¬ÆÉ¤ß¼è¤ê¤Ç¤¢¤Ã¤¿¡¥ - * 1 = ¥Õ¥©¥ë¥È¤Î¸¶°ø¤È¤Ê¤Ã¤¿¥¢¥¯¥»¥¹¤¬½ñ¤­¹þ¤ß¤Ç¤¢¤Ã¤¿¡¥ - * 0: P: 0 = ¥Õ¥©¥ë¥È¤Î¸¶°ø¤¬ÉԺߥڡ¼¥¸¤Ç¤¢¤Ã¤¿¡¥ - * 1 = ¥Õ¥©¥ë¥È¤Î¸¶°ø¤¬¥Ú¡¼¥¸¡¦¥ì¥Ù¥ëÊݸî°ãÈ¿¤Ç¤¢¤Ã¤¿¡¥ + * 4-31: äººÑ¤ß + * 3: RSVD: 0 = ¥Õ¥©¥ë¥È¤Î¸¶°ø¤ÏͽÌó¥Ó¥Ã¥È°ãÈ¿¤Ç¤Ï¤Ê¤«¤Ã¤¿¡¥ + * 1 = ¥Ú¡¼¥¸¡¦¥Õ¥©¥ë¥È¤Î¸¶°ø¤Ï¡¤°ãÈ¿¤È¥Þ¡¼¥¯¤µ¤ì¤¿ PTE ¤Þ¤¿¤Ï + * PDE ¤ÎͽÌó¥Ó¥Ã¥È°ÌÃ֤Τ¦¤Á°ì¤Ä¤Ç¡¤1 ¤¬¸¡½Ð¤µ¤ì¤¿¤³¤È¤Ç¤¢¤ë¡¥ + * 2: U/S: 0 = ¥Õ¥©¥ë¥È¤Î¸¶°ø¤È¤Ê¤Ã¤¿¥¢¥¯¥»¥¹¤Ï¥×¥í¥»¥Ã¥µ¤¬¥¹¡¼¥Ñ¥Ð¥¤¥¶¡¦ + * ¥â¡¼¥É¤Ç¼Â¹ÔÃæ¤Ë¹Ô¤ï¤ì¤¿¡¥ + * 1 = ¥Õ¥©¥ë¥È¤Î¸¶°ø¤È¤Ê¤Ã¤¿¥¢¥¯¥»¥¹¤Ï¥×¥í¥»¥Ã¥µ¤¬¥æ¡¼¥¶¡¦¥â¡¼¥É¤Ç + * ¼Â¹ÔÃæ¤Ë¹Ô¤ï¤ì¤¿¡¥ + * 1: W/R: 0 = ¥Õ¥©¥ë¥È¤Î¸¶°ø¤È¤Ê¤Ã¤¿¥¢¥¯¥»¥¹¤¬ÆÉ¤ß¼è¤ê¤Ç¤¢¤Ã¤¿¡¥ + * 1 = ¥Õ¥©¥ë¥È¤Î¸¶°ø¤È¤Ê¤Ã¤¿¥¢¥¯¥»¥¹¤¬½ñ¤­¹þ¤ß¤Ç¤¢¤Ã¤¿¡¥ + * 0: P: 0 = ¥Õ¥©¥ë¥È¤Î¸¶°ø¤¬ÉԺߥڡ¼¥¸¤Ç¤¢¤Ã¤¿¡¥ + * 1 = ¥Õ¥©¥ë¥È¤Î¸¶°ø¤¬¥Ú¡¼¥¸¡¦¥ì¥Ù¥ëÊݸî°ãÈ¿¤Ç¤¢¤Ã¤¿¡¥ */ /* - * ²¼´¬ 4.12. ¥Ú¡¼¥¸Êݸî¤È¥»¥°¥á¥ó¥ÈÊݸî¤ÎÁȤ߹ç¤ï¤» - * ¡Öɽ 4-2. ¥Ú¡¼¥¸¡¦¥Ç¥£¥ì¥¯¥È¥ê¤È¥Ú¡¼¥¸¡¦¥Æ¡¼¥Ö¥ë¤ÎÊݸî¤ÎÁȤ߹ç¤ï¤»¡× + * ä¸ 4.12. ¥Ú¡¼¥¸Êݸî¤È¥»¥°¥á¥ó¥ÈÊݸî¤ÎÁȤ߹ç¤ï¤» + * ¡Öɽ 4-2. ¥Ú¡¼¥¸¡¦¥Ç¥£¥ì¥¯¥È¥ê¤È¥Ú¡¼¥¸¡¦¥Æ¡¼¥Ö¥ë¤ÎÊݸî¤ÎÁȤ߹ç¤ï¤»¡× * * +------------+------------+------------+ * | PDE | PTE | merge | @@ -75,11 +71,11 @@ * | s | rw | s | rw | s | rw | * +-----+------+-----+------+-----+------+ * - * ¡Ö¥£ rw/p : CR0 ¡¢¥Û WP ¡¦¥â¡¦¥Æ¡¦¥Í¡¢¥ã ON ¡¢¥Û¥»ø»î¦¥Ò¡¢¥Þ ro + * ãॵ rw/p : CR0 åá¥ç WP åãÆå¥ãåã°å¡ì ON åá¥çꢥ¨éð°å¢­åá¥Ã ro */ /* - * ¡¦â§ä§ô§¡Ö¡¦¥Ã¡¦¥µ¡¦¥±/PxE(¥»ê·¥å¥µ¥¤¥»¥Í)/CPL/CR0 ¡¢¥Í¡¦¥ì¡£¥·¡¦¥¯¡¦¡Ö¡¦¥Ã¡¦¥µ¡¦¥±¥¯¡Ö¡¢¥Û¥¨¥ê¥­¥¯ + * åã¡£åã¡Öå㥧åâ¡Öåâ¥Ãå⥵å⥱/PxE(躴ꥣÐç½âí奡)/CPL/CR0 åᥣåãÔ妾å⥯åâ¡Öåâ¥Ãå⥵å⥱쪥¥åá¥çñö¡ÖèÁ * * +-----+-----+-----+-----+-----+---+ * | CR0 | CPL | PxE | PxE | ope | | @@ -159,17 +155,17 @@ static const UINT8 page_access_bit[32] = /* *-- - * 32bit ʪÍý¥¢¥É¥ì¥¹ 4k ¥Ú¡¼¥¸ + * 32bit í饥íð¬å¤¤åã²å¦®å⥱ 4k åãÔ妾å⥯ * - * ¡¦ô§¥Ò¡¦¡Ö¡£¥ò¡¦¡Ö¡¦¥Î¡¦ø§¥± + * å㥧åã¶å¤¤å㥵åâ¡Öåã²å¦®å⥱ * 31 22 21 12 11 0 * +------------------------+----------------------+--------------------------+ - * | ¡¦¥ì¡£¥·¡¦¥¯¡£¥ò¡¦¥Ì¡¦¡×¡¦ø§¥Ã¡¦¥Í¡¦ | ¥Ú¡¼¥¸¡¦¥Æ¡¼¥Ö¥ë | ¥ª¥Õ¥»¥Ã¥È | + * | åãÔ妾å⥯å㥵åã®å¤¥åã¥ãåâ¥Ãåã°å¦¬ | åãÔ妾å⥯å㥵åã¬å¦¾åãÌ妭 | å⥧åãÊ夽åã¦å¥è | * +------------------------+----------------------+--------------------------+ * | | | * +-----------+ +-----------+ +----------+ * | | | - * | ¡¦¥ì¡£¥·¡¦¥¯¡£¥ò¡¦¥Ì¡¦¡×¡¦ø§¥Ã¡¦¥Í¡¦ | ¥Ú¡¼¥¸¡¦¥Æ¡¼¥Ö¥ë ¥Ú¡¼¥¸ | + * | ¥Ú¡¼¥¸¡¦¥Ç¥£¥ì¥¯¥È¥ê | ¥Ú¡¼¥¸¡¦¥Æ¡¼¥Ö¥ë ¥Ú¡¼¥¸ | * | +--------------------+ | +-------------------+ +------------------+ | * | | | | | | | | | * | | | | +-------------------+ | | | @@ -181,442 +177,654 @@ static const UINT8 page_access_bit[32] = * | | | | | | | | * +>+--------------------+ +>+-------------------+ +>+------------------+ * | - * +- CR3() + * +- CR3(ʪÍý¥¢¥É¥ì¥¹) */ -static UINT32 paging(const UINT32 laddr, const int ucrw); -#if defined(IA32_SUPPORT_TLB) -static BOOL tlb_lookup(const UINT32 vaddr, const int crw, UINT32 *paddr); -static void tlb_update(const UINT32 laddr, const UINT entry, const int crw); -#endif +/* TLB */ +struct tlb_entry { + UINT32 tag; /* linear address */ +#define TLB_ENTRY_TAG_VALID (1 << 0) +/* pde & pte & CPU_PTE_WRITABLE (1 << 1) */ +/* pde & pte & CPU_PTE_USER_MODE (1 << 2) */ +#define TLB_ENTRY_TAG_DIRTY CPU_PTE_DIRTY /* (1 << 6) */ +#define TLB_ENTRY_TAG_GLOBAL CPU_PTE_GLOBAL_PAGE /* (1 << 8) */ +#define TLB_ENTRY_TAG_MAX_SHIFT 12 + UINT32 paddr; /* physical address */ +}; +static void MEMCALL tlb_update(UINT32 laddr, UINT entry, int ucrw); + +/* paging */ +static UINT32 MEMCALL paging(UINT32 laddr, int ucrw); -#if defined(IA32_PAGING_EACHSIZE) +/* + * linear memory access + */ +/* RMW */ UINT8 MEMCALL -cpu_memory_access_la_RMW_b(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg) +cpu_memory_access_la_RMW_b(UINT32 laddr, UINT32 (CPUCALL *func)(UINT32, void *), void *arg) { - const int ucrw = CPU_PAGE_WRITE|CPU_PAGE_DATA|CPU_STAT_USER_MODE; - UINT32 result, value; + const int ucrw = CPU_PAGE_WRITE_DATA | CPU_STAT_USER_MODE; + struct tlb_entry *ep; UINT32 paddr; + UINT32 result; + UINT8 value; + /* TLB */ + ep = tlb_lookup(laddr, ucrw); + if (ep != NULL) { + paddr = ep->paddr + (laddr & CPU_PAGE_MASK); + goto onepage; + } + + /* paging */ paddr = paging(laddr, ucrw); +onepage: value = cpu_memoryread(paddr); result = (*func)(value, arg); cpu_memorywrite(paddr, (UINT8)result); - return value; } UINT16 MEMCALL -cpu_memory_access_la_RMW_w(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg) +cpu_memory_access_la_RMW_w(UINT32 laddr, UINT32 (CPUCALL *func)(UINT32, void *), void *arg) { - const int ucrw = CPU_PAGE_WRITE|CPU_PAGE_DATA|CPU_STAT_USER_MODE; - UINT32 result, value; + const int ucrw = CPU_PAGE_WRITE_DATA | CPU_STAT_USER_MODE; + struct tlb_entry *ep[2]; UINT32 paddr[2]; + UINT32 result; + UINT16 value; + /* TLB */ + ep[0] = tlb_lookup(laddr, ucrw); + if (ep[0] != NULL) { + paddr[0] = ep[0]->paddr + (laddr & CPU_PAGE_MASK); + if ((laddr + 1) & CPU_PAGE_MASK) + goto onepage; + + ep[1] = tlb_lookup(laddr + 1, ucrw); + if (ep[1] != NULL) { + paddr[1] = ep[1]->paddr + (laddr & CPU_PAGE_MASK); + goto separate; + } + } + + /* paging */ paddr[0] = paging(laddr, ucrw); - if ((laddr + 1) & 0x00000fff) { + if ((laddr + 1) & CPU_PAGE_MASK) { +onepage: value = cpu_memoryread_w(paddr[0]); result = (*func)(value, arg); cpu_memorywrite_w(paddr[0], (UINT16)result); - } else { - paddr[1] = paging(laddr + 1, ucrw); - value = cpu_memoryread_b(paddr[0]); - value += (UINT16)cpu_memoryread_b(paddr[1]) << 8; - result = (*func)(value, arg); - cpu_memorywrite(paddr[0], (UINT8)result); - cpu_memorywrite(paddr[1], (UINT8)(result >> 8)); + return value; } + + paddr[1] = paging(laddr + 1, ucrw); +separate: + value = cpu_memoryread_b(paddr[0]); + value += (UINT16)cpu_memoryread_b(paddr[1]) << 8; + result = (*func)(value, arg); + cpu_memorywrite(paddr[0], (UINT8)result); + cpu_memorywrite(paddr[1], (UINT8)(result >> 8)); return value; } UINT32 MEMCALL -cpu_memory_access_la_RMW_d(UINT32 laddr, UINT32 (*func)(UINT32, void *), void *arg) +cpu_memory_access_la_RMW_d(UINT32 laddr, UINT32 (CPUCALL *func)(UINT32, void *), void *arg) { - const int ucrw = CPU_PAGE_WRITE|CPU_PAGE_DATA|CPU_STAT_USER_MODE; - UINT32 result, value; + const int ucrw = CPU_PAGE_WRITE_DATA | CPU_STAT_USER_MODE; + struct tlb_entry *ep[2]; UINT32 paddr[2]; - UINT remain; + UINT32 result; + UINT32 value; + int remain; + /* TLB */ + ep[0] = tlb_lookup(laddr, ucrw); + if (ep[0] != NULL) { + paddr[0] = ep[0]->paddr + (laddr & CPU_PAGE_MASK); + remain = CPU_PAGE_SIZE - (laddr & CPU_PAGE_MASK); + if (remain >= 4) + goto onepage; + + ep[1] = tlb_lookup(laddr + remain, ucrw); + if (ep[1] != NULL) { + paddr[1] = ep[1]->paddr + (laddr & CPU_PAGE_MASK); + goto separate; + } + } + + /* paging */ paddr[0] = paging(laddr, ucrw); - remain = 0x1000 - (laddr & 0x00000fff); + remain = CPU_PAGE_SIZE - (laddr & CPU_PAGE_MASK); if (remain >= 4) { +onepage: value = cpu_memoryread_d(paddr[0]); result = (*func)(value, arg); cpu_memorywrite_d(paddr[0], result); - } else { - paddr[1] = paging(laddr + remain, ucrw); - switch (remain) { - case 3: - value = cpu_memoryread(paddr[0]); - value += (UINT32)cpu_memoryread_w(paddr[0] + 1) << 8; - value += (UINT32)cpu_memoryread(paddr[1]) << 24; - result = (*func)(value, arg); - cpu_memorywrite(paddr[0], (UINT8)result); - cpu_memorywrite_w(paddr[0] + 1, (UINT16)(result >> 8)); - cpu_memorywrite(paddr[1], (UINT8)(result >> 24)); - break; + return value; + } - case 2: - value = cpu_memoryread_w(paddr[0]); - value += (UINT32)cpu_memoryread_w(paddr[1]) << 16; - result = (*func)(value, arg); - cpu_memorywrite_w(paddr[0], (UINT16)result); - cpu_memorywrite_w(paddr[1], (UINT16)(result >> 16)); - break; + paddr[1] = paging(laddr + remain, ucrw); +separate: + switch (remain) { + case 3: + value = cpu_memoryread(paddr[0]); + value += (UINT32)cpu_memoryread_w(paddr[0] + 1) << 8; + value += (UINT32)cpu_memoryread(paddr[1]) << 24; + result = (*func)(value, arg); + cpu_memorywrite(paddr[0], (UINT8)result); + cpu_memorywrite_w(paddr[0] + 1, (UINT16)(result >> 8)); + cpu_memorywrite(paddr[1], (UINT8)(result >> 24)); + break; - case 1: - value = cpu_memoryread(paddr[0]); - value += (UINT32)cpu_memoryread_w(paddr[1]) << 8; - value += (UINT32)cpu_memoryread(paddr[1] + 2) << 24; - result = (*func)(value, arg); - cpu_memorywrite(paddr[0], (UINT8)result); - cpu_memorywrite_w(paddr[1], (UINT16)(result >> 8)); - cpu_memorywrite(paddr[1] + 2, (UINT8)(result >> 24)); - break; + case 2: + value = cpu_memoryread_w(paddr[0]); + value += (UINT32)cpu_memoryread_w(paddr[1]) << 16; + result = (*func)(value, arg); + cpu_memorywrite_w(paddr[0], (UINT16)result); + cpu_memorywrite_w(paddr[1], (UINT16)(result >> 16)); + break; - default: - ia32_panic("cpu_memory_access_la_RMW_d(): out of range (remain = %d)\n", remain); - value = 0; /* compiler happy */ - break; - } + case 1: + value = cpu_memoryread(paddr[0]); + value += (UINT32)cpu_memoryread_w(paddr[1]) << 8; + value += (UINT32)cpu_memoryread(paddr[1] + 2) << 24; + result = (*func)(value, arg); + cpu_memorywrite(paddr[0], (UINT8)result); + cpu_memorywrite_w(paddr[1], (UINT16)(result >> 8)); + cpu_memorywrite(paddr[1] + 2, (UINT8)(result >> 24)); + break; + + default: + ia32_panic("cpu_memory_access_la_RMW_d: out of range (remain=%d)\n", remain); + value = 0; /* XXX compiler happy */ + break; } return value; } +/* read */ UINT8 MEMCALL -cpu_linear_memory_read_b(UINT32 laddr, const int ucrw) +cpu_linear_memory_read_b(UINT32 laddr, int ucrw) { - UINT32 addr; + struct tlb_entry *ep; + UINT32 paddr; - addr = paging(laddr, ucrw); - return cpu_memoryread(addr); + /* TLB */ + ep = tlb_lookup(laddr, ucrw); + if (ep != NULL) { + paddr = ep->paddr + (laddr & CPU_PAGE_MASK); + return cpu_memoryread(paddr); + } + + /* paging */ + paddr = paging(laddr, ucrw); + return cpu_memoryread(paddr); } UINT16 MEMCALL -cpu_linear_memory_read_w(UINT32 laddr, const int ucrw) +cpu_linear_memory_read_w(UINT32 laddr, int ucrw) { - UINT32 addr, addr2; + struct tlb_entry *ep[2]; + UINT32 paddr[2]; UINT16 value; - addr = paging(laddr, ucrw); - if ((laddr + 1) & 0x00000fff) { - return cpu_memoryread_w(addr); - } else { - addr2 = paging(laddr + 1, ucrw); - value = cpu_memoryread_b(addr); - value += (UINT16)cpu_memoryread_b(addr2) << 8; - return value; + /* TLB */ + ep[0] = tlb_lookup(laddr, ucrw); + if (ep[0] != NULL) { + paddr[0] = ep[0]->paddr + (laddr & CPU_PAGE_MASK); + if ((laddr + 1) & CPU_PAGE_MASK) + return cpu_memoryread_w(paddr[0]); + + ep[1] = tlb_lookup(laddr + 1, ucrw); + if (ep[1] != NULL) { + paddr[1] = ep[1]->paddr; + goto separate; + } } + + /* paging */ + paddr[0] = paging(laddr, ucrw); + if ((laddr + 1) & CPU_PAGE_MASK) + return cpu_memoryread_w(paddr[0]); + + paddr[1] = paging(laddr + 1, ucrw); +separate: + value = cpu_memoryread_b(paddr[0]); + value += (UINT16)cpu_memoryread_b(paddr[1]) << 8; + return value; } UINT32 MEMCALL -cpu_linear_memory_read_d(UINT32 laddr, const int ucrw) +cpu_linear_memory_read_d(UINT32 laddr, int ucrw) { - UINT32 addr, addr2; + struct tlb_entry *ep[2]; + UINT32 paddr[2]; UINT32 value; UINT remain; - addr = paging(laddr, ucrw); - remain = 0x1000 - (laddr & 0x00000fff); - if (remain >= 4) { - return cpu_memoryread_d(addr); - } else { - addr2 = paging(laddr + remain, ucrw); - switch (remain) { - case 3: - value = cpu_memoryread(addr); - value += (UINT32)cpu_memoryread_w(addr + 1) << 8; - value += (UINT32)cpu_memoryread(addr2) << 24; - break; - - case 2: - value = cpu_memoryread_w(addr); - value += (UINT32)cpu_memoryread_w(addr2) << 16; - break; - - case 1: - value = cpu_memoryread(addr); - value += (UINT32)cpu_memoryread(addr2) << 8; - value += (UINT32)cpu_memoryread_w(addr2 + 1) << 16; - break; - - default: - ia32_panic("cpu_linear_memory_read_d(): out of range (remain = %d)\n", remain); - value = 0; /* compiler happy */ - break; + /* TLB */ + ep[0] = tlb_lookup(laddr, ucrw); + if (ep[0] != NULL) { + paddr[0] = ep[0]->paddr + (laddr & CPU_PAGE_MASK); + remain = CPU_PAGE_SIZE - (laddr & CPU_PAGE_MASK); + if (remain >= sizeof(value)) + return cpu_memoryread_d(paddr[0]); + + ep[1] = tlb_lookup(laddr + remain, ucrw); + if (ep[1] != NULL) { + paddr[1] = ep[1]->paddr; + goto separate; } - return value; } -} -void MEMCALL -cpu_linear_memory_write_b(UINT32 laddr, UINT8 value, const int user_mode) -{ - const int ucrw = CPU_PAGE_WRITE|CPU_PAGE_DATA|user_mode; - UINT32 addr; + /* paging */ + paddr[0] = paging(laddr, ucrw); + remain = CPU_PAGE_SIZE - (laddr & CPU_PAGE_MASK); + if (remain >= sizeof(value)) + return cpu_memoryread_d(paddr[0]); - addr = paging(laddr, ucrw); - cpu_memorywrite(addr, value); -} + paddr[1] = paging(laddr + remain, ucrw); +separate: + switch (remain) { + case 3: + value = cpu_memoryread(paddr[0]); + value += (UINT32)cpu_memoryread_w(paddr[0] + 1) << 8; + value += (UINT32)cpu_memoryread(paddr[1]) << 24; + break; -void MEMCALL -cpu_linear_memory_write_w(UINT32 laddr, UINT16 value, const int user_mode) -{ - const int ucrw = CPU_PAGE_WRITE|CPU_PAGE_DATA|user_mode; - UINT32 addr, addr2; + case 2: + value = cpu_memoryread_w(paddr[0]); + value += (UINT32)cpu_memoryread_w(paddr[1]) << 16; + break; + + case 1: + value = cpu_memoryread(paddr[0]); + value += (UINT32)cpu_memoryread_w(paddr[1]) << 8; + value += (UINT32)cpu_memoryread(paddr[1] + 2) << 24; + break; - addr = paging(laddr, ucrw); - if ((laddr + 1) & 0x00000fff) { - cpu_memorywrite_w(addr, value); - } else { - addr2 = paging(laddr + 1, ucrw); - cpu_memorywrite(addr, (UINT8)value); - cpu_memorywrite(addr2, (UINT8)(value >> 8)); + default: + ia32_panic("cpu_linear_memory_read_d: out of range (remain=%d)\n", remain); + value = 0; /* XXX compiler happy */ + break; } + return value; } -void MEMCALL -cpu_linear_memory_write_d(UINT32 laddr, UINT32 value, const int user_mode) +UINT64 MEMCALL +cpu_linear_memory_read_q(UINT32 laddr, int ucrw) { - const int ucrw = CPU_PAGE_WRITE|CPU_PAGE_DATA|user_mode; - UINT32 addr, addr2; + struct tlb_entry *ep[2]; + UINT32 paddr[2]; + UINT64 value; UINT remain; - addr = paging(laddr, ucrw); - remain = 0x1000 - (laddr & 0x00000fff); - if (remain >= 4) { - cpu_memorywrite_d(addr, value); - } else { - addr2 = paging(laddr + remain, ucrw); - switch (remain) { - case 3: - cpu_memorywrite(addr, (UINT8)value); - cpu_memorywrite_w(addr + 1, (UINT16)(value >> 8)); - cpu_memorywrite(addr2, (UINT8)(value >> 24)); - break; - - case 2: - cpu_memorywrite_w(addr, (UINT16)value); - cpu_memorywrite_w(addr2, (UINT16)(value >> 16)); - break; - - case 1: - cpu_memorywrite(addr, (UINT8)value); - cpu_memorywrite(addr2, (UINT8)(value >> 8)); - cpu_memorywrite_w(addr2 + 1, (UINT16)(value >> 16)); - break; + /* TLB */ + ep[0] = tlb_lookup(laddr, ucrw); + if (ep[0] != NULL) { + paddr[0] = ep[0]->paddr + (laddr & CPU_PAGE_MASK); + remain = CPU_PAGE_SIZE - (laddr & CPU_PAGE_MASK); + if (remain >= sizeof(value)) + return cpu_memoryread_d(paddr[0]); + + ep[1] = tlb_lookup(laddr + remain, ucrw); + if (ep[1] != NULL) { + paddr[1] = ep[1]->paddr; + goto separate; } } -} - -#else /* !IA32_PAGING_EACHSIZE */ - -UINT32 MEMCALL -cpu_memory_access_la_RMW(UINT32 laddr, UINT length, UINT32 (*func)(UINT32, void *), void *arg) -{ - const int ucrw = CPU_PAGE_WRITE|CPU_PAGE_DATA|CPU_STAT_USER_MODE; - UINT32 result, value; - UINT32 paddr[2]; - UINT remain; + /* paging */ paddr[0] = paging(laddr, ucrw); - remain = 0x1000 - (laddr & 0x00000fff); - if (remain >= length) { - /* fast mode */ - switch (length) { - case 4: - value = cpu_memoryread_d(paddr[0]); - result = (*func)(value, arg); - cpu_memorywrite_d(paddr[0], result); - break; + remain = CPU_PAGE_SIZE - (laddr & CPU_PAGE_MASK); + if (remain >= sizeof(value)) + return cpu_memoryread_q(paddr[0]); - case 2: - value = cpu_memoryread_w(paddr[0]); - result = (*func)(value, arg); - cpu_memorywrite_w(paddr[0], (UINT16)result); - break; + paddr[1] = paging(laddr + remain, ucrw); +separate: + switch (remain) { + case 7: + value = cpu_memoryread(paddr[0]); + value += (UINT64)cpu_memoryread_w(paddr[0] + 1) << 8; + value += (UINT64)cpu_memoryread_d(paddr[0] + 3) << 24; + value += (UINT64)cpu_memoryread(paddr[1]) << 56; + break; - case 1: - value = cpu_memoryread(paddr[0]); - result = (*func)(value, arg); - cpu_memorywrite(paddr[0], (UINT8)result); - break; + case 6: + value = cpu_memoryread_w(paddr[0]); + value += (UINT64)cpu_memoryread_d(paddr[0] + 2) << 16; + value += (UINT64)cpu_memoryread_w(paddr[1]) << 48; + break; - default: - ia32_panic("cpu_memory_access_la_RMW(): invalid length (length = %d)\n", length); - value = 0; /* compiler happy */ - break; - } - return value; - } + case 5: + value = cpu_memoryread(paddr[0]); + value += (UINT64)cpu_memoryread_d(paddr[0] + 1) << 8; + value += (UINT64)cpu_memoryread_w(paddr[1]) << 40; + value += (UINT64)cpu_memoryread(paddr[1] + 2) << 56; + break; + + case 4: + value = cpu_memoryread_d(paddr[0]); + value += (UINT64)cpu_memoryread_d(paddr[1]) << 32; + break; - /* slow mode */ - paddr[1] = paging(laddr + remain, ucrw); - switch (remain) { case 3: value = cpu_memoryread(paddr[0]); - value += (UINT32)cpu_memoryread_w(paddr[0] + 1) << 8; - value += (UINT32)cpu_memoryread(paddr[1]) << 24; - result = (*func)(value, arg); - cpu_memorywrite(paddr[0], (UINT8)result); - cpu_memorywrite_w(paddr[0] + 1, (UINT16)(result >> 8)); - cpu_memorywrite(paddr[1], (UINT8)(result >> 24)); + value += (UINT64)cpu_memoryread_w(paddr[0] + 1) << 8; + value += (UINT64)cpu_memoryread_d(paddr[1]) << 24; + value += (UINT64)cpu_memoryread(paddr[1] + 4) << 56; break; case 2: value = cpu_memoryread_w(paddr[0]); - value += (UINT32)cpu_memoryread_w(paddr[1]) << 16; - result = (*func)(value, arg); - cpu_memorywrite_w(paddr[0], (UINT16)result); - cpu_memorywrite_w(paddr[1], (UINT16)(result >> 16)); + value += (UINT64)cpu_memoryread_d(paddr[1]) << 16; + value += (UINT64)cpu_memoryread_w(paddr[1] + 4) << 48; break; case 1: value = cpu_memoryread(paddr[0]); - value += (UINT32)cpu_memoryread(paddr[1]) << 8; - if (length == 4) { - value += (UINT32)cpu_memoryread_w(paddr[1] + 1) << 16; - } - result = (*func)(value, arg); - cpu_memorywrite(paddr[0], (UINT8)result); - cpu_memorywrite(paddr[1], (UINT8)(result >> 8)); - if (length == 4) { - cpu_memorywrite_w(paddr[1] + 1, (UINT16)(result >> 16)); - } + value += (UINT64)cpu_memoryread_d(paddr[1]) << 8; + value += (UINT64)cpu_memoryread_w(paddr[1] + 4) << 40; + value += (UINT64)cpu_memoryread(paddr[1] + 6) << 56; break; default: - ia32_panic("cpu_memory_access_la_RMW(): out of range (remain = %d)\n", remain); - value = 0; /* compiler happy */ + ia32_panic("cpu_linear_memory_read_q: out of range (remain=%d)\n", remain); + value = 0; /* XXX compiler happy */ break; } return value; } -UINT32 MEMCALL -cpu_linear_memory_read(UINT32 laddr, UINT length, const int ucrw) +REG80 MEMCALL +cpu_linear_memory_read_f(UINT32 laddr, int ucrw) { - UINT32 value; + struct tlb_entry *ep[2]; UINT32 paddr[2]; + REG80 value; UINT remain; + UINT i, j; + + /* TLB */ + ep[0] = tlb_lookup(laddr, ucrw); + if (ep[0] != NULL) { + paddr[0] = ep[0]->paddr + (laddr & CPU_PAGE_MASK); + remain = CPU_PAGE_SIZE - (laddr & CPU_PAGE_MASK); + if (remain >= sizeof(value)) + return cpu_memoryread_f(paddr[0]); + + ep[1] = tlb_lookup(laddr + remain, ucrw); + if (ep[1] != NULL) { + paddr[1] = ep[1]->paddr; + goto separate; + } + } + /* paging */ paddr[0] = paging(laddr, ucrw); - remain = 0x1000 - (laddr & 0x00000fff); - if (remain >= length) { - /* fast mode */ - switch (length) { - case 4: - value = cpu_memoryread_d(paddr[0]); - break; + remain = CPU_PAGE_SIZE - (laddr & CPU_PAGE_MASK); + if (remain >= sizeof(value)) + return cpu_memoryread_f(paddr[0]); - case 2: - value = cpu_memoryread_w(paddr[0]); - break; + paddr[1] = paging(laddr + remain, ucrw); +separate: + for (i = 0; i < remain; ++i) { + value.b[i] = cpu_memoryread(paddr[0] + i); + } + for (j = 0; i < 10; ++i, ++j) { + value.b[i] = cpu_memoryread(paddr[1] + j); + } + return value; +} - case 1: - value = cpu_memoryread(paddr[0]); - break; +/* write */ +void MEMCALL +cpu_linear_memory_write_b(UINT32 laddr, UINT8 value, int ucrw) +{ + struct tlb_entry *ep; + UINT32 paddr; - default: - ia32_panic("cpu_linear_memory_read(): invalid length (length = %d)\n", length); - value = 0; /* compiler happy */ - break; + /* TLB */ + ep = tlb_lookup(laddr, ucrw); + if (ep != NULL) { + paddr = ep->paddr + (laddr & CPU_PAGE_MASK); + cpu_memorywrite(paddr, value); + return; + } + + /* paging */ + paddr = paging(laddr, ucrw); + cpu_memorywrite(paddr, value); +} + +void MEMCALL +cpu_linear_memory_write_w(UINT32 laddr, UINT16 value, int ucrw) +{ + struct tlb_entry *ep[2]; + UINT32 paddr[2]; + + /* TLB */ + ep[0] = tlb_lookup(laddr, ucrw); + if (ep[0] != NULL) { + paddr[0] = ep[0]->paddr + (laddr & CPU_PAGE_MASK); + if ((laddr + 1) & CPU_PAGE_MASK) { + cpu_memorywrite_w(paddr[0], value); + return; + } + + ep[1] = tlb_lookup(laddr + 1, ucrw); + if (ep[1] != NULL) { + paddr[1] = ep[1]->paddr; + goto separate; } - return value; } - /* slow mode */ + /* paging */ + paddr[0] = paging(laddr, ucrw); + if ((laddr + 1) & CPU_PAGE_MASK) { + cpu_memorywrite_w(paddr[0], value); + return; + } + + paddr[1] = paging(laddr + 1, ucrw); +separate: + cpu_memorywrite(paddr[0], (UINT8)value); + cpu_memorywrite(paddr[1], (UINT8)(value >> 8)); +} + +void MEMCALL +cpu_linear_memory_write_d(UINT32 laddr, UINT32 value, int ucrw) +{ + struct tlb_entry *ep[2]; + UINT32 paddr[2]; + UINT remain; + + /* TLB */ + ep[0] = tlb_lookup(laddr, ucrw); + if (ep[0] != NULL) { + paddr[0] = ep[0]->paddr + (laddr & CPU_PAGE_MASK); + remain = CPU_PAGE_SIZE - (laddr & CPU_PAGE_MASK); + if (remain >= sizeof(value)) { + cpu_memorywrite_d(paddr[0], value); + return; + } + + ep[1] = tlb_lookup(laddr + remain, ucrw); + if (ep[1] != NULL) { + paddr[1] = ep[1]->paddr; + goto separate; + } + } + + /* paging */ + paddr[0] = paging(laddr, ucrw); + remain = CPU_PAGE_SIZE - (laddr & CPU_PAGE_MASK); + if (remain >= sizeof(value)) { + cpu_memorywrite_d(paddr[0], value); + return; + } + paddr[1] = paging(laddr + remain, ucrw); +separate: switch (remain) { case 3: - value = cpu_memoryread(paddr[0]); - value += (UINT32)cpu_memoryread_w(paddr[0] + 1) << 8; - value += (UINT32)cpu_memoryread(paddr[1]) << 24; + cpu_memorywrite(paddr[0], (UINT8)value); + cpu_memorywrite_w(paddr[0] + 1, (UINT16)(value >> 8)); + cpu_memorywrite(paddr[1], (UINT8)(value >> 24)); break; case 2: - value = cpu_memoryread_w(paddr[0]); - value += (UINT32)cpu_memoryread_w(paddr[1]) << 16; + cpu_memorywrite_w(paddr[0], (UINT16)value); + cpu_memorywrite_w(paddr[1], (UINT16)(value >> 16)); break; case 1: - value = cpu_memoryread(paddr[0]); - value += (UINT32)cpu_memoryread(paddr[1]) << 8; - if (length == 4) { - value += (UINT32)cpu_memoryread_w(paddr[1] + 1) << 16; - } + cpu_memorywrite(paddr[0], (UINT8)value); + cpu_memorywrite_w(paddr[1], (UINT16)(value >> 8)); + cpu_memorywrite(paddr[1] + 2, (UINT8)(value >> 24)); break; default: - ia32_panic("cpu_linear_memory_read(): out of range (remain = %d)\n", remain); - value = 0; /* compiler happy */ + ia32_panic("cpu_linear_memory_write_d: out of range (remain=%d)\n", remain); break; } - return value; } void MEMCALL -cpu_linear_memory_write(UINT32 laddr, UINT32 value, UINT length, const int user_mode) +cpu_linear_memory_write_q(UINT32 laddr, UINT64 value, int ucrw) { - const int ucrw = CPU_PAGE_WRITE|CPU_PAGE_DATA|user_mode; + struct tlb_entry *ep[2]; UINT32 paddr[2]; UINT remain; - paddr[0] = paging(laddr, ucrw); - remain = 0x1000 - (laddr & 0x00000fff); - if (remain >= length) { - /* fast mode */ - switch (length) { - case 4: - cpu_memorywrite_d(paddr[0], value); - break; - - case 2: - cpu_memorywrite_w(paddr[0], (UINT16)value); - break; - - case 1: - cpu_memorywrite(paddr[0], (UINT8)value); - break; + /* TLB */ + ep[0] = tlb_lookup(laddr, ucrw); + if (ep[0] != NULL) { + paddr[0] = ep[0]->paddr + (laddr & CPU_PAGE_MASK); + remain = CPU_PAGE_SIZE - (laddr & CPU_PAGE_MASK); + if (remain >= sizeof(value)) { + cpu_memorywrite_q(paddr[0], value); + return; + } - default: - ia32_panic("cpu_linear_memory_write(): invalid length (length = %d)\n", length); - break; + ep[1] = tlb_lookup(laddr + remain, ucrw); + if (ep[1] != NULL) { + paddr[1] = ep[1]->paddr; + goto separate; } + } + + /* paging */ + paddr[0] = paging(laddr, ucrw); + remain = CPU_PAGE_SIZE - (laddr & CPU_PAGE_MASK); + if (remain >= sizeof(value)) { + cpu_memorywrite_q(paddr[0], value); return; } - /* slow mode */ paddr[1] = paging(laddr + remain, ucrw); +separate: switch (remain) { + case 7: + cpu_memorywrite(paddr[0], (UINT8)value); + cpu_memorywrite_w(paddr[0] + 1, (UINT16)(value >> 8)); + cpu_memorywrite_d(paddr[0] + 3, (UINT32)(value >> 24)); + cpu_memorywrite(paddr[1], (UINT8)(value >> 56)); + break; + + case 6: + cpu_memorywrite_w(paddr[0], (UINT16)value); + cpu_memorywrite_d(paddr[0] + 2, (UINT32)(value >> 16)); + cpu_memorywrite_w(paddr[1], (UINT16)(value >> 48)); + break; + + case 5: + cpu_memorywrite(paddr[0], (UINT8)value); + cpu_memorywrite_d(paddr[0] + 1, (UINT32)(value >> 8)); + cpu_memorywrite_w(paddr[1], (UINT16)(value >> 40)); + cpu_memorywrite(paddr[1] + 2, (UINT8)(value >> 56)); + break; + + case 4: + cpu_memorywrite_d(paddr[0], (UINT32)value); + cpu_memorywrite_d(paddr[1], (UINT32)(value >> 32)); + break; + case 3: cpu_memorywrite(paddr[0], (UINT8)value); cpu_memorywrite_w(paddr[0] + 1, (UINT16)(value >> 8)); - cpu_memorywrite(paddr[1], (UINT8)(value >> 24)); + cpu_memorywrite_d(paddr[1], (UINT32)(value >> 24)); + cpu_memorywrite(paddr[1] + 4, (UINT8)(value >> 56)); break; case 2: cpu_memorywrite_w(paddr[0], (UINT16)value); - cpu_memorywrite_w(paddr[1], (UINT16)(value >> 16)); + cpu_memorywrite_d(paddr[1], (UINT32)(value >> 16)); + cpu_memorywrite_w(paddr[1] + 4, (UINT16)(value >> 48)); break; case 1: cpu_memorywrite(paddr[0], (UINT8)value); - cpu_memorywrite(paddr[1], (UINT8)(value >> 8)); - if (length == 4) { - cpu_memorywrite_w(paddr[1] + 1, (UINT16)(value >> 16)); - } + cpu_memorywrite_d(paddr[1], (UINT32)(value >> 8)); + cpu_memorywrite_w(paddr[1] + 4, (UINT16)(value >> 40)); + cpu_memorywrite(paddr[1] + 6, (UINT8)(value >> 56)); break; default: - ia32_panic("cpu_linear_memory_write(): out of range (remain = %d)\n", remain); + ia32_panic("cpu_linear_memory_write_q: out of range (remain=%d)\n", remain); break; } } -#endif /* IA32_PAGING_EACHSIZE */ void MEMCALL -cpu_memory_access_la_region(UINT32 laddr, UINT length, const int ucrw, BYTE *data) +cpu_linear_memory_write_f(UINT32 laddr, const REG80 *value, int ucrw) +{ + struct tlb_entry *ep[2]; + UINT32 paddr[2]; + UINT remain; + UINT i, j; + + /* TLB */ + ep[0] = tlb_lookup(laddr, ucrw); + if (ep[0] != NULL) { + paddr[0] = ep[0]->paddr + (laddr & CPU_PAGE_MASK); + remain = CPU_PAGE_SIZE - (laddr & CPU_PAGE_MASK); + if (remain >= sizeof(value)) { + cpu_memorywrite_f(paddr[0], value); + return; + } + + ep[1] = tlb_lookup(laddr + remain, ucrw); + if (ep[1] != NULL) { + paddr[1] = ep[1]->paddr; + goto separate; + } + } + + /* paging */ + paddr[0] = paging(laddr, ucrw); + remain = CPU_PAGE_SIZE - (laddr & CPU_PAGE_MASK); + if (remain >= sizeof(value)) { + cpu_memorywrite_f(paddr[0], value); + return; + } + + paddr[1] = paging(laddr + remain, ucrw); +separate: + for (i = 0; i < remain; ++i) { + cpu_memorywrite(paddr[0] + i, value->b[i]); + } + for (j = 0; i < 10; ++i, ++j) { + cpu_memorywrite(paddr[1] + j, value->b[i]); + } +} + +/* + * linear address memory access function + */ +void MEMCALL +cpu_memory_access_la_region(UINT32 laddr, UINT length, int ucrw, UINT8 *data) { UINT32 paddr; UINT remain; /* page remain */ @@ -625,7 +833,7 @@ cpu_memory_access_la_region(UINT32 laddr if (length == 0) return; - remain = 0x1000 - (laddr & 0x00000fff); + remain = CPU_PAGE_SIZE - (laddr & CPU_PAGE_MASK); for (;;) { if (!CPU_STAT_PAGING) { paddr = laddr; @@ -649,39 +857,23 @@ cpu_memory_access_la_region(UINT32 laddr remain -= r; if (remain <= 0) { /* next page */ - remain += 0x1000; + remain += CPU_PAGE_SIZE; } } } -void MEMCALL -paging_check(UINT32 laddr, UINT length, const int ucrw) +UINT32 MEMCALL +laddr2paddr(UINT32 laddr, int ucrw) { - UINT32 paddr; - UINT remain; /* page remain */ - UINT r; - remain = 0x1000 - (laddr & 0x00000fff); - for (;;) { - paddr = paging(laddr, ucrw); - - r = (remain > length) ? length : remain; - - length -= r; - if (length == 0) - break; - - laddr += r; - remain -= r; - if (remain <= 0) { - /* next page */ - remain += 0x1000; - } - } + return paging(laddr, ucrw); } -static UINT32 -paging(const UINT32 laddr, const int ucrw) +/* + * paging + */ +static UINT32 MEMCALL +paging(UINT32 laddr, int ucrw) { UINT32 paddr; /* physical address */ UINT32 pde_addr; /* page directory entry address */ @@ -690,11 +882,11 @@ paging(const UINT32 laddr, const int ucr UINT32 pte; /* page table entry */ UINT bit; UINT err; + struct tlb_entry *ep; -#if defined(IA32_SUPPORT_TLB) - if (tlb_lookup(laddr, crw, &paddr)) - return paddr; -#endif /* IA32_SUPPORT_TLB */ + ep = tlb_lookup(laddr, ucrw); + if (ep != NULL) + return ep->paddr + (laddr & CPU_PAGE_MASK); pde_addr = CPU_STAT_PDE_BASE + ((laddr >> 20) & 0xffc); pde = cpu_memoryread_d(pde_addr); @@ -725,11 +917,10 @@ paging(const UINT32 laddr, const int ucr } /* make physical address */ - paddr = (pte & CPU_PTE_BASEADDR_MASK) + (laddr & 0x00000fff); + paddr = (pte & CPU_PTE_BASEADDR_MASK) + (laddr & CPU_PAGE_MASK); - bit = ucrw & CPU_PAGE_WRITE; + bit = ucrw & (CPU_PAGE_WRITE|CPU_PAGE_USER_MODE); bit |= (pde & pte & (CPU_PTE_WRITABLE|CPU_PTE_USER_MODE)); - bit |= ucrw & CPU_PAGE_USER_MODE; bit |= CPU_STAT_WP; #if !defined(USE_PAGE_ACCESS_TABLE) @@ -751,9 +942,7 @@ paging(const UINT32 laddr, const int ucr cpu_memorywrite_d(pte_addr, pte); } -#if defined(IA32_SUPPORT_TLB) - tlb_update(laddr, pte, ucrw); -#endif /* IA32_SUPPORT_TLB */ + tlb_update(laddr, pte, (bit & (CPU_PTE_WRITABLE|CPU_PTE_USER_MODE)) + ((ucrw & CPU_PAGE_CODE) ? 1 : 0)); return paddr; @@ -765,182 +954,140 @@ pf_exception: return 0; /* compiler happy */ } - -#if defined(IA32_SUPPORT_TLB) /* * TLB */ -#if defined(IA32_PROFILE_TLB) -/* profiling */ -typedef struct { - UINT64 tlb_hits; - UINT64 tlb_misses; - UINT64 tlb_lookups; - UINT64 tlb_updates; - UINT64 tlb_flushes; - UINT64 tlb_global_flushes; - UINT64 tlb_entry_flushes; -} TLB_PROFILE_T; - -static TLB_PROFILE_T tlb_profile; - -#define PROFILE_INC(v) tlb_profile.v++ -#else /* !IA32_PROFILE_TLB */ -#define PROFILE_INC(v) -#endif /* IA32_PROFILE_TLB */ - - -typedef struct { - UINT32 tag; /* linear address */ -#define TLB_ENTRY_VALID (1 << 0) -#define TLB_ENTRY_GLOBAL CPU_PTE_GLOBAL_PAGE - - UINT32 paddr; /* physical address */ -} TLB_ENTRY_T; - -#define TLB_GET_PADDR(ep, addr) ((ep)->paddr + ((addr) & ~CPU_PTE_BASEADDR_MASK)) -#define TLB_SET_PADDR(ep, addr) ((ep)->paddr = (addr) & CPU_PTE_BASEADDR_MASK) - -#define TLB_TAG_SHIFT 17 -#define TLB_TAG_MASK ~((1 << TLB_TAG_SHIFT) - 1) +#define TLB_TAG_SHIFT TLB_ENTRY_TAG_MAX_SHIFT +#define TLB_TAG_MASK (~((1 << TLB_TAG_SHIFT) - 1)) #define TLB_GET_TAG_ADDR(ep) ((ep)->tag & TLB_TAG_MASK) #define TLB_SET_TAG_ADDR(ep, addr) \ - ((ep)->tag = ((addr) & TLB_TAG_MASK) + ((ep)->tag & ~TLB_TAG_MASK)) - -#define TLB_IS_VALID(ep) ((ep)->tag & TLB_ENTRY_VALID) -#define TLB_SET_VALID(ep) ((ep)->tag |= TLB_ENTRY_VALID) -#define TLB_CLEAR_VALID(ep) ((ep)->tag &= ~TLB_ENTRY_VALID) - -#if CPU_FAMILY == 4 -#define TLB_IS_GLOBAL(ep) FALSE -#define TLB_SET_GLOBAL(ep) (void)(ep) -#define TLB_CLEAR_GLOBAL(ep) (void)(ep) +do { \ + (ep)->tag &= ~TLB_TAG_MASK; \ + (ep)->tag |= (addr) & TLB_TAG_MASK; \ +} while (/*CONSTCOND(*/ 0) + +#define TLB_IS_VALID(ep) ((ep)->tag & TLB_ENTRY_TAG_VALID) +#define TLB_SET_VALID(ep) ((ep)->tag = TLB_ENTRY_TAG_VALID) +#define TLB_SET_INVALID(ep) ((ep)->tag = 0) + +#define TLB_IS_WRITABLE(ep) ((ep)->tag & CPU_PTE_WRITABLE) +#define TLB_IS_USERMODE(ep) ((ep)->tag & CPU_PTE_USER_MODE) +#define TLB_IS_DIRTY(ep) ((ep)->tag & TLB_ENTRY_TAG_DIRTY) +#if (CPU_FEATURES & CPU_FEATURE_PGE) == CPU_FEATURE_PGE +#define TLB_IS_GLOBAL(ep) ((ep)->tag & TLB_ENTRY_TAG_GLOBAL) #else -#define TLB_IS_GLOBAL(ep) ((ep)->tag & TLB_ENTRY_GLOBAL) -#define TLB_SET_GLOBAL(ep) ((ep)->tag |= TLB_ENTRY_GLOBAL) -#define TLB_CLEAR_GLOBAL(ep) ((ep)->tag &= ~TLB_ENTRY_GLOBAL) +#define TLB_IS_GLOBAL(ep) 0 #endif +#define TLB_SET_TAG_FLAGS(ep, entry, bit) \ +do { \ + (ep)->tag |= (entry) & (CPU_PTE_GLOBAL_PAGE|CPU_PTE_DIRTY); \ + (ep)->tag |= (bit) & (CPU_PTE_WRITABLE|CPU_PTE_USER_MODE); \ +} while (/*CONSTCOND*/ 0) -#if CPU_FAMILY == 4 -#define NTLB 1 -#define NENTRY (1 << 3) -#define NWAY (1 << 2) - +#define NTLB 2 /* 0: DTLB, 1: ITLB */ +#define NENTRY (1 << 6) #define TLB_ENTRY_SHIFT 12 #define TLB_ENTRY_MASK (NENTRY - 1) -#define TLB_WAY_SHIFT 15 -#define TLB_WAY_MASK (NWAY - 1) -#endif typedef struct { - TLB_ENTRY_T entry[NENTRY][NWAY]; -} TLB_T; - -static TLB_T tlb; - + struct tlb_entry entry[NENTRY]; +} tlb_t; +static tlb_t tlb[NTLB]; void tlb_init(void) { - memset(&tlb, 0, sizeof(tlb)); -#if defined(IA32_PROFILE_TLB) - memset(&tlb_profile, 0, sizeof(tlb_profile)); -#endif /* IA32_PROFILE_TLB */ + memset(tlb, 0, sizeof(tlb)); } -void +void MEMCALL tlb_flush(BOOL allflush) { - TLB_ENTRY_T *ep; - int i, j; + struct tlb_entry *ep; + int i; + int n; if (allflush) { - PROFILE_INC(tlb_global_flushes); - } else { - PROFILE_INC(tlb_flushes); + tlb_init(); + return; } - for (i = 0; i < NENTRY ; i++) { - for (j = 0; j < NWAY; j++) { - ep = &tlb.entry[i][j]; - if (TLB_IS_VALID(ep) && (!TLB_IS_GLOBAL(ep) || allflush)) { - TLB_CLEAR_VALID(ep); - PROFILE_INC(tlb_entry_flushes); + for (n = 0; n < NTLB; n++) { + for (i = 0; i < NENTRY ; i++) { + ep = &tlb[n].entry[i]; + if (TLB_IS_VALID(ep) && !TLB_IS_GLOBAL(ep)) { + TLB_SET_INVALID(ep); } } } } -void +void MEMCALL tlb_flush_page(UINT32 laddr) { - TLB_ENTRY_T *ep; + struct tlb_entry *ep; int idx; - int way; - - PROFILE_INC(tlb_flushes); + int n; - idx = (laddr >> TLB_ENTRY_SHIFT) & (NENTRY - 1); - way = (laddr >> TLB_WAY_SHIFT) & (NWAY - 1); - ep = &tlb.entry[idx][way]; + idx = (laddr >> TLB_ENTRY_SHIFT) & TLB_ENTRY_MASK; - if (TLB_IS_VALID(ep)) { - if ((laddr & TLB_TAG_MASK) == TLB_GET_TAG_ADDR(ep)) { - TLB_CLEAR_VALID(ep); - return; + for (n = 0; n < NTLB; n++) { + ep = &tlb[n].entry[idx]; + if (TLB_IS_VALID(ep)) { + if ((laddr & TLB_TAG_MASK) == TLB_GET_TAG_ADDR(ep)) { + TLB_SET_INVALID(ep); + } } } } -static BOOL -tlb_lookup(const UINT32 laddr, const int crw, UINT32 *paddr) +struct tlb_entry * MEMCALL +tlb_lookup(UINT32 laddr, int ucrw) { - TLB_ENTRY_T *ep; + struct tlb_entry *ep; + UINT bit; int idx; - int way; - - PROFILE_INC(tlb_lookups); + int n; - idx = (laddr >> TLB_ENTRY_SHIFT) & (NENTRY - 1); - way = (laddr >> TLB_WAY_SHIFT) & (NWAY - 1); - ep = &tlb.entry[idx][way]; + n = (ucrw & CPU_PAGE_CODE) ? 1 : 0; + idx = (laddr >> TLB_ENTRY_SHIFT) & TLB_ENTRY_MASK; + ep = &tlb[n].entry[idx]; - ep = &tlb.entry[idx][way]; if (TLB_IS_VALID(ep)) { if ((laddr & TLB_TAG_MASK) == TLB_GET_TAG_ADDR(ep)) { - *paddr = TLB_GET_PADDR(ep, laddr); - PROFILE_INC(tlb_hits); - return TRUE; + bit = ucrw & (CPU_PAGE_WRITE|CPU_PAGE_USER_MODE); + bit |= ep->tag & (CPU_PTE_WRITABLE|CPU_PTE_USER_MODE); + bit |= CPU_STAT_WP; +#if !defined(USE_PAGE_ACCESS_TABLE) + if ((page_access & (1 << bit))) +#else + if (page_access_bit[bit]) +#endif + { + if (!(ucrw & CPU_PAGE_WRITE) || TLB_IS_DIRTY(ep)) { + return ep; + } + } } } - (void)crw; - PROFILE_INC(tlb_misses); - return FALSE; + return NULL; } -static void -tlb_update(const UINT32 laddr, const UINT entry, const int crw) +static void MEMCALL +tlb_update(UINT32 laddr, UINT entry, int bit) { - TLB_ENTRY_T *ep; + struct tlb_entry *ep; int idx; - int way; - - PROFILE_INC(tlb_updates); + int n; - idx = (laddr >> TLB_ENTRY_SHIFT) & (NENTRY - 1); - way = (laddr >> TLB_WAY_SHIFT) & (NWAY - 1); - ep = &tlb.entry[idx][way]; + n = bit & 1; + idx = (laddr >> TLB_ENTRY_SHIFT) & TLB_ENTRY_MASK; + ep = &tlb[n].entry[idx]; TLB_SET_VALID(ep); -#if CPU_FAMILY >= 5 - if (entry & CPU_PTE_GLOBAL_PAGE) { - TLB_SET_GLOBAL(ep); - } -#endif TLB_SET_TAG_ADDR(ep, laddr); - TLB_SET_PADDR(ep, entry); - (void)crw; + TLB_SET_TAG_FLAGS(ep, entry, bit); + ep->paddr = entry & CPU_PTE_BASEADDR_MASK; } -#endif /* IA32_SUPPORT_TLB */