--- np2/i386c/ia32/paging.c	2004/01/23 16:17:51	1.5
+++ np2/i386c/ia32/paging.c	2004/02/03 14:27:07	1.8
@@ -1,4 +1,4 @@
-/*	$Id: paging.c,v 1.5 2004/01/23 16:17:51 monaka Exp $	*/
+/*	$Id: paging.c,v 1.8 2004/02/03 14:27:07 monaka Exp $	*/
 
 /*
  * Copyright (c) 2003 NONAKA Kimihiro
@@ -112,7 +112,7 @@
  * +-----+-----------+-----+-----+---+
  */
 #if !defined(USE_PAGE_ACCESS_TABLE)
-static const DWORD page_access = 0xd0cdd0ff;
+#define	page_access	0xd0ddd0ff
 #else	/* USE_PAGE_ACCESS_TABLE */
 static const BYTE page_access_bit[32] = {
 	1,	/* CR0: n, CPL: s, PTE: s, PTE: r, ope: r */
@@ -143,7 +143,7 @@ static const BYTE page_access_bit[32] = 
 	1,	/* CR0: p, CPL: s, PTE: u, PTE: r, ope: r */
 	0,	/* CR0: p, CPL: s, PTE: u, PTE: r, ope: w */
 	1,	/* CR0: p, CPL: s, PTE: u, PTE: w, ope: r */
-	0,	/* CR0: p, CPL: s, PTE: u, PTE: w, ope: w */
+	1,	/* CR0: p, CPL: s, PTE: u, PTE: w, ope: w */
 
 	0,	/* CR0: p, CPL: u, PTE: s, PTE: r, ope: r */
 	0,	/* CR0: p, CPL: u, PTE: s, PTE: r, ope: w */
@@ -239,14 +239,16 @@ cpu_linear_memory_read(DWORD laddr, DWOR
 			break;
 		}
 
-		if (length == r)
+		length -= r;
+		if (length == 0)
 			break;
 
 		laddr += r;
-		length -= r;
 		remain -= r;
-		if (remain <= 0)
+		if (remain <= 0) {
+			/* next page */
 			remain += 0x1000;
+		}
 	}
 
 	return value;
@@ -285,7 +287,7 @@ cpu_linear_memory_write(DWORD laddr, DWO
 		case 3:
 			cpu_memorywrite_w(paddr, value & 0xffff);
 			value >>= 16;
-			cpu_memorywrite(paddr, value & 0xff);
+			cpu_memorywrite(paddr + 2, value & 0xff);
 			value >>= 8;
 			break;
 
@@ -298,14 +300,16 @@ cpu_linear_memory_write(DWORD laddr, DWO
 			break;
 		}
 
-		if (length == r)
+		length -= r;
+		if (length == 0)
 			break;
 
 		laddr += r;
-		length -= r;
 		remain -= r;
-		if (remain <= 0)
+		if (remain <= 0) {
+			/* next page */
 			remain += 0x1000;
+		}
 	}
 }
 
@@ -327,14 +331,17 @@ paging_check(DWORD laddr, DWORD length, 
 		paddr = paging(laddr, crw, pl);
 
 		r = (remain > length) ? length : remain;
-		if (length == r)
+
+		length -= r;
+		if (length == 0)
 			break;
 
 		laddr += r;
-		length -= r;
 		remain -= r;
-		if (remain <= 0)
+		if (remain <= 0) {
+			/* next page */
 			remain += 0x1000;
+		}
 	}
 }
 
@@ -347,7 +354,7 @@ paging(DWORD laddr, int crw, int user_mo
 	DWORD pte_addr;	/* page table entry address */
 	DWORD pte;	/* page table entry */
 	DWORD bit;
-	DWORD err = 0;
+	DWORD err;
 
 #if defined(IA32_SUPPORT_TLB)
 	if (tlb_lookup(laddr, crw, &paddr))
@@ -368,6 +375,7 @@ paging(DWORD laddr, int crw, int user_mo
 		cpu_memorywrite_d(pde_addr, pde);
 	}
 
+#if CPU_FAMILY >= 5
 	/* no support PAE */
 	__ASSERT(!(CPU_CR4 & CPU_CR4_PAE));
 
@@ -380,7 +388,9 @@ paging(DWORD laddr, int crw, int user_mo
 
 		/* make physical address */
 		paddr = (pde & CPU_PDE_4M_BASEADDR_MASK) | (laddr & 0x003fffff);
-	} else {
+	} else
+#endif	/* CPU_FAMILY >= 5 */
+	{
 		/* 4KB page size */
 		pte_addr = (pde & CPU_PDE_BASEADDR_MASK) | ((laddr >> 10) & 0xffc);
 		pte = cpu_memoryread_d(pte_addr);