--- np2/i386c/ia32/paging.c	2004/01/27 15:56:57	1.7
+++ np2/i386c/ia32/paging.c	2004/02/03 14:49:39	1.9
@@ -1,4 +1,4 @@
-/*	$Id: paging.c,v 1.7 2004/01/27 15:56:57 monaka Exp $	*/
+/*	$Id: paging.c,v 1.9 2004/02/03 14:49:39 monaka Exp $	*/
 
 /*
  * Copyright (c) 2003 NONAKA Kimihiro
@@ -112,7 +112,7 @@
  * +-----+-----------+-----+-----+---+
  */
 #if !defined(USE_PAGE_ACCESS_TABLE)
-static const DWORD page_access = 0xd0cdd0ff;
+#define	page_access	0xd0ddd0ff
 #else	/* USE_PAGE_ACCESS_TABLE */
 static const BYTE page_access_bit[32] = {
 	1,	/* CR0: n, CPL: s, PTE: s, PTE: r, ope: r */
@@ -143,7 +143,7 @@ static const BYTE page_access_bit[32] = 
 	1,	/* CR0: p, CPL: s, PTE: u, PTE: r, ope: r */
 	0,	/* CR0: p, CPL: s, PTE: u, PTE: r, ope: w */
 	1,	/* CR0: p, CPL: s, PTE: u, PTE: w, ope: r */
-	0,	/* CR0: p, CPL: s, PTE: u, PTE: w, ope: w */
+	1,	/* CR0: p, CPL: s, PTE: u, PTE: w, ope: w */
 
 	0,	/* CR0: p, CPL: u, PTE: s, PTE: r, ope: r */
 	0,	/* CR0: p, CPL: u, PTE: s, PTE: r, ope: w */
@@ -213,27 +213,25 @@ cpu_linear_memory_read(DWORD laddr, DWOR
 
 		r = (remain > length) ? length : remain;
 		switch (r) {
-		case 1:
-			value |= (DWORD)cpu_memoryread(paddr) << shift;
-			shift += 8;
+		case 4:
+			value = cpu_memoryread_d(paddr);
 			break;
 
+		case 3:
+			value |= (DWORD)cpu_memoryread(paddr) << shift;
+			shift += 8;
+			paddr++;
+			/*FALLTHROUGH*/
 		case 2:
 			value |= (DWORD)cpu_memoryread_w(paddr) << shift;
 			shift += 16;
 			break;
 
-		case 3:
-			value |= (DWORD)cpu_memoryread_w(paddr) << shift;
-			shift += 16;
-			value |= (DWORD)cpu_memoryread(paddr + 2) << shift;
+		case 1:
+			value |= (DWORD)cpu_memoryread(paddr) << shift;
 			shift += 8;
 			break;
 
-		case 4:
-			value = cpu_memoryread_d(paddr);
-			break;
-
 		default:
 			ia32_panic("cpu_linear_memory_read(): out of range (r = %d)\n", r);
 			break;
@@ -255,7 +253,7 @@ cpu_linear_memory_read(DWORD laddr, DWOR
 }
 
 void MEMCALL
-cpu_linear_memory_write(DWORD laddr, DWORD length, DWORD value)
+cpu_linear_memory_write(DWORD laddr, DWORD value, DWORD length)
 {
 	DWORD paddr;
 	DWORD remain;	/* page remain */
@@ -274,27 +272,25 @@ cpu_linear_memory_write(DWORD laddr, DWO
 
 		r = (remain > length) ? length : remain;
 		switch (r) {
-		case 1:
-			cpu_memorywrite(paddr, value & 0xff);
-			value >>= 8;
+		case 4:
+			cpu_memorywrite_d(paddr, value);
 			break;
 
+		case 3:
+			cpu_memorywrite(paddr, value & 0xff);
+			value >>= 8;
+			paddr++;
+			/*FALLTHROUGH*/
 		case 2:
 			cpu_memorywrite_w(paddr, value & 0xffff);
 			value >>= 16;
 			break;
 
-		case 3:
-			cpu_memorywrite_w(paddr, value & 0xffff);
-			value >>= 16;
-			cpu_memorywrite(paddr + 2, value & 0xff);
+		case 1:
+			cpu_memorywrite(paddr, value & 0xff);
 			value >>= 8;
 			break;
 
-		case 4:
-			cpu_memorywrite_d(paddr, value);
-			break;
-
 		default:
 			ia32_panic("cpu_linear_memory_write(): out of range (r = %d)\n", r);
 			break;
@@ -361,7 +357,7 @@ paging(DWORD laddr, int crw, int user_mo
 		return paddr;
 #endif	/* IA32_SUPPORT_TLB */
 
-	pde_addr = (CPU_CR3 & CPU_CR3_PD_MASK) | ((laddr >> 20) & 0xffc);
+	pde_addr = CPU_STAT_PDE_BASE | ((laddr >> 20) & 0xffc);
 	pde = cpu_memoryread_d(pde_addr);
 	if (!(pde & CPU_PDE_PRESENT)) {
 		VERBOSE(("paging: PDE is not present"));
@@ -375,6 +371,7 @@ paging(DWORD laddr, int crw, int user_mo
 		cpu_memorywrite_d(pde_addr, pde);
 	}
 
+#if CPU_FAMILY >= 5
 	/* no support PAE */
 	__ASSERT(!(CPU_CR4 & CPU_CR4_PAE));
 
@@ -387,7 +384,9 @@ paging(DWORD laddr, int crw, int user_mo
 
 		/* make physical address */
 		paddr = (pde & CPU_PDE_4M_BASEADDR_MASK) | (laddr & 0x003fffff);
-	} else {
+	} else
+#endif	/* CPU_FAMILY >= 5 */
+	{
 		/* 4KB page size */
 		pte_addr = (pde & CPU_PDE_BASEADDR_MASK) | ((laddr >> 10) & 0xffc);
 		pte = cpu_memoryread_d(pte_addr);